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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-13701-7E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90570 Series MB90573/574/574C/F574/F574A/V570/V570A s DESCRIPTION The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real time processing. It contains an I2C*2 bus interface that allows inter-equipment communication to be implemented readily. This product is well adapted to car audio equipment, VTR systems, and other equipment and systems. The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit free run timer, an input capture (ICU), an output compare (OCU)). *1: F2MC stands for FUJITSU Flexible Microcontroller. *2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. s PACKAGE 120-pin plastic LQFP 120-pin plastic QFP 120-pin plastic LQFP ( ) (FPT-120P-M05) (FPT-120P-M13) (FPT-120P-M21) MB90570 Series s FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from 1/2 to 4x oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4x PLL clock, operation at VCC of 5.0 V) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 16 channels * Embedded ROM size and types Mask ROM: 128 kbytes/256 kbytes Flash ROM: 256 kbytes Embedded RAM size: 6 kbytes/10 kbytes (mask ROM) 10 kbytes (flash memory) 10 kbytes (evaluation device) * Low-power consumption (standby) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware standby mode * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 63 ports General-purpose I/O ports (with pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 10 ports Total: 97 ports (Continued) 2 MB90570 Series (Continued) * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel * 8/16-bit up/down counter/timer: 1 channel (8-bit x 2 channels) * 16-bit I/O timer 16-bit free run timer: 1 channel Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon detection of an edge input to the pin. Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free run timer counter value and the compare setting value. * Extended I/O serial interface: 3 channels * I2C interface (1 channel) Serial I/O port for supporting Inter IC BUS * UART0 (SCI), UART1 (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used. * DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution Starting by an external trigger input. Conversion time: 26.3 s * 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent) Setup time: 12.5 s * Clock timer: 1 channel * Chip select output (8 channels) An active level can be set. * Clock output function 3 MB90570 Series s PRODUCT LINEUP Part number Item Classification ROM size RAM size MB90573 MB90574/C MB90F574/A MB90V570/A Mask ROM products 128 kbytes 6 kbytes Flash ROM products Evaluation product 256 kbytes 10 kbytes None CPU functions The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 63 General-purpose I/O ports (with pull-up resistor): 24 General-purpose I/O ports (N-ch open-drain output): 10 Total: 97 Clock synchronized transmission (62.5 kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Resolution: 8/10-bit Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 1 (or 8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 s (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 (or 8-bit x 2 channels) Event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel Number of channel: 1 Overflow interrupts Number of channels: 4 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Ports UART0 (SCI), UART1 (SCI) 8/10-bit A/D converter 8/16-bit PPG timer 8/16-bit up/down counter/ timer 16-bit free run timer 16-bit I/O timer Output compare (OCU) Input capture (ICU) (Continued) 4 MB90570 Series (Continued) Part number Item DTP/external interrupt circuit Delayed interrupt generation module Extended I/O serial interface I2C interface Timebase timer Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. An interrupt generation module for switching tasks used in real time operating systems. Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first Serial I/O port for supporting Inter IC BUS 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/clock timer/hardware standby CMOS 4.5 V to 5.5 V MB90573 MB90574/C MB90F574/A MB90V570/A 8-bit D/A converter Watchdog timer Low-power consumption (standby) mode Process Power supply voltage for operation* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25C, and an operating frequency of 1 MHz to 16 MHz. s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-120P-M05 FPT-120P-M13 FPT-120P-M21 : Available x: Not available Note: For more information about each package, see section "s Package Dimensions." x x MB90573 MB90574 MB90F574/A MB90574C x 5 MB90570 Series s DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V570/A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) * In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. * The products designated with /A or /C are different from those without /A or /C in that they are DTP/externallyinterrupted types which return from standby mode at the ch.0 to ch.1 edge request. 6 MB90570 Series s PIN ASSIGNMENT (Top view) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK VCC P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1 P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3 P56/IN0 P57/IN1 P60/SIN4 P61/SOT4 P62/SCK4 P63/CKOT P64/OUT0 P65/OUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P30/ALE VSS P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS RST MD0 MD1 MD2 HST PC3 PC2 PC1 PC0 PB7 PB6/ADTG PB5/IRQ5 PB4/IRQ4 PB3/IRQ3 PB2/IRQ2 PB1/IRQ1 X0A X1A PB0/IRQ0 PA7/SCL PA6/SDA PA5/ZIN1 PA4/BIN1 PA3/AIN1/IRQ7 PA2/ZIN0 PA1/BIN0 PA0/AIN0/IRQ6 VSS P97/CS7 P96/CS6 P66/OUT2 P67/OUT3 VSS C P70 P71 P72 DVCC DVSS P73/DA0 P74/DA1 AVCC AVRH AVRL AVSS P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 VCC P90/CS0 P91/CS1 P92/CS2 P93/CS3 P94/CS4 P95/CS5 (FPT-120P-M05) (FPT-120P-M13) (FPT-120P-M21) 7 MB90570 Series s PIN DESCRIPTION Pin no. LQFP-120 *1 QFP-120 *2 92,93 74,73 89 to 87 90 86 95 to 102 Pin name X0,X1 X0A,X1A MD0 to MD2 RST HST P00 to P07 Circuit type A B C C C D High speed oscillator input pins Low speed oscillator input pins These are input pins used to designate the operating mode. They should be connected directly to Vcc or Vss. Reset input pin Hardware standby input pin In single chip mode, these are general purpose I/O pins. When set for input, they can be set by the pull-up resistance setting register (RDR0). When set for output, this setting will be invalid. In external bus mode, these pins function as address low output/data low I/O pins. Function AD00 to AD07 103 to 110 P10 to P17 D In single chip mode, these are general purpose I/O pins. When set for input, they can be set by the pull-up resistance setting register (RDR1). When set for output, the setting will be invalid. In external bus mode, these pins function as address middle output/data high I/O pins. AD08 to AD15 111 to 118 120 P20 to P27 A16 to A23 P30 ALE 1 P31 RD 2 P32 WRL 3 P33 WRH 4 P34 HRQ 5 P35 HAK 6 P36 RDY *1: FPT-120P-M05 *2: FPT-120P-M13,FPT-120P-M21 E E E E E E E E In single chip mode this is a general-purpose I/O port. In external bus mode, these pins function as address high output pins. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the address latch enable signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the read strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus lower 8-bit write strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus upper 8-bit write strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold request signal input pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold acknowledge signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the ready signal input pin. (Continued) 8 MB90570 Series Pin no. LQFP-120 *1 QFP-120 *2 7 Pin name P37 CLK 9 P40 SIN0 F Circuit type E Function In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the clock (CLK) signal output pin. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.0 serial data input pin. While UART ch.0 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation. 10 P41 SOT0 F In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.0 serial data output pin. This function is valid when UART ch.0 is enabled for data output. 11 P42 SCK0 F In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.0 serial clock I/O pin. This function is valid when UART ch.0 is enabled for clock output. 12 P43 SIN1 F In single chip mode this is a general-purpose I/O port. It can be set to open-drain by the ODR4 register. This is also the UART ch.1 serial data input pin. While UART ch.1 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation. 13 P44 SOT1 F In single chip mode this is a general-purpose I/O port. It can be set to opendrain by the ODR4 register. This is also the UART ch.1 serial data output pin. This function is valid when UART ch.1 is enabled for data output. 14 P45 SCK1 F In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.1 serial clock I/O pin. This function is valid when UART ch.1 is enabled for clock output. 15,16 P46,P47 PPG0,PPG1 F In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. These are also the PPG0, 1 output pins. This function is valid when PPG0, 1 output is enabled. 17 P50 SIN2 E In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 data input pin. During serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. *1: FPT-120P-M05 *2: FPT-120P-M13,FPT-120P-M21 (Continued) 9 MB90570 Series Pin no. LQFP-120 *1 QFP-120 *2 18 Pin name P51 SOT2 19 P52 SCK2 20 P53 SIN3 21 P54 SOT3 22 P55 SCK3 23,24 P56,P57 IN0,IN1 25 P60 SIN4 26 P61 SOT4 27 P62 SCK4 28 P63 CKOT *1: FPT-120P-M05 *2: FPT-120P-M13,FPT-120P-M21 F F F F E E E E E Circuit type E Function In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 data output pin. This function is valid when serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 clock I/O pin. This function is valid when serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 data input pin. During serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 data output pin. This function is valid when serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 clock I/O pin. This function is valid when serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. These are also the input capture ch.0/1 trigger input pins. During input capture signal input on ch.0/1 this function is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 data input pin. During serial data input this function is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 data output pin. This function is valid when serial ch.2 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 serial clock I/O pin. This function is valid when serial ch.2 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the clock monitor output pin. This function is valid when clock monitor output is enabled. (Continued) 10 MB90570 Series Pin no. LQFP-120 *1 QFP-120 *2 29 to 32 Pin name P64 to P67 OUT0 to OUT3 35 to 37 40,41 46 to 53 P70 to P72 P73,P74 DA0,DA1 P80 to P87 AN0 to AN7 55 to 62 P90 to P97 CS0 to CS7 34 64 C PA0 AIN0 IRQ6 65 PA1 BIN0 66 PA2 ZIN0 67 PA3 AIN1 IRQ7 68 PA4 BIN1 69 PA5 ZIN1 *1: FPT-120P-M05 *2: FPT-120P-M13,FPT-120P-M21 E E E E E G E E K E I Circuit type F Function In single chip mode these are general-purpose I/O ports. When set for input they can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. These are also the output compare ch.0 to ch.3 event output pins. This function is valid when the respective channel(s) are enabled for output. These are general purpose I/O ports. These are general purpose I/O ports. These are also the D/A converter ch.0,1 analog signal output pins. These are general purpose I/O ports. These are also A/D converter analog input pins. This function is valid when analog input is enabled. These are general purpose I/O ports. These are also chip select signal output pins. This function is valid when chip select signal output is enabled. This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. Note that this is not required on the FLASH model (MB90F574/A) and MB90574C. This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter ch.0. This pin can also be used as interrupt request input ch. 6. This is a general purpose I/O port. This pin is also used as count clock B input for 8/16-bit up-down counter ch.0. This is a general purpose I/O port. This pin is also used as count clock Z input for 8/16-bit up-down counter ch.0. This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter ch.1. This pin can also be used as interrupt request input ch.7. This is a general purpose I/O port. This pin is also used as count clock B input for 8/16-bit up-down counter ch.1. This is a general purpose I/O port. This pin is also used as count clock Z input for 8/16-bit up-down counter ch.1. (Continued) 11 MB90570 Series (Continued) Pin no. LQFP-120 *1 QFP-120 *2 70 Pin name PA6 SDA Circuit type L Function This is a general purpose I/O port. This pin is also used as the data I/O pin for the I2C interface. This function is valid when the I2C interface is enabled for operation. While the I2C interface is operating, this port should be set to the input level (DDRA: bit6 = 0). 71 PA7 SCL L This is a general purpose I/O port. This pin is also used as the clock I/O pin for the I2C interface. This function is valid when the I2C interface is enabled for operation. While the I2C interface is operating, this port should be set to the input level (DDRA: bit7 = 0). 72, 75 to 79 PB0, PB1 to PB5 IRQ0, IRQ1 to IRQ5 E These are general-purpose I/O ports. These pins are also the external interrupt input pins. IRQ0, 1 are enabled for both rising and falling edge detection, and therefore cannot be used for recovery from STOP status for MB90V570, MB90F574, MB90573 and MB90574. However, IRQ0, 1 can be used for recovery from STOP status for MB90V570A, MB90F574A and MB90574C. 80 PB6 ADTG E This is a general purpose I/O port. This is also the A/D converter external trigger input pin. While the A/D converter is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. 81 82 to 85 8,54,94 33,63, 91,119 42 43 44 45 38 39 PB7 PC0 to PC3 VCC VSS AVCC AVRH AVRL AVSS DVCC DVSS E E Power supply Power supply H J H H H H This is a general purpose I/O port. These are general purpose I/O ports. These are power supply (5V) input pins. These are power supply (0V) input pins. This is the analog macro (D/A, A/D etc.) Vcc power supply input pin. This is the A/D converter Vref+ input pin. The input voltage should not exceed Vcc. This is the A/D converter Vref-input pin. The input voltage should not less than Vss. This is the analog macro (D/A, A/D etc.) Vss power supply input pin. This is the D/A converter Vref input pin. The input voltage should not exceed Vcc. This is the D/A converter GND power supply pin. It should be set to Vss equivalent potential. *1: FPT-120P-M05 *2: FPT-120P-M13,FPT-120P-M21 12 MB90570 Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks * Oscillator circuit Oscillator recovery resistance for high speed = approx. 1 M X0 Standby control signal B X1A * Oscillator circuit Oscillator recovery resistance for low speed = approx. 1 M X0A Standby control signal C R Hysteresis input * Hysteresis input pin Resistance value = approx. 50 k (typ.) D VCC VCC P-ch P-ch Selective signal either with a pull-up resistor or without it. N-ch R Hysteresis input Standby control for input interruption IOL = 4 mA * CMOS hysteresis input pin with input pullup control * CMOS level output. * CMOS hysteresis input (Includes input shut down standby control function) * Pull-up resistance value = approx. 50 k(typ.) IOL = 4mA (Continued) 13 MB90570 Series Type E Circuit VCC P-ch Remarks * CMOS hysteresis input/output pin. * CMOS level output * CMOS hysteresis input (Includes input shut down standby control function) IOL = 4 mA Hysteresis input N-ch R Standby control for input interruption IOL = 4 mA F VCC P-ch N-ch R Hysteresis input Standby control for input interruption * CMOS hysteresis input/output pin. * CMOS level output * CMOS hysteresis input (Includes input shut down standby control function) IOL = 10 mA (Large current port) IOL = 10 mA G VCC * C pin output (capacitance connector pin). P-ch N-ch On the MB90F574 this pin is not connected (NC). H VCC * Analog power supply protector circuit. P-ch AVP N-ch I VCC P-ch N-ch R Hysteresis input Standby control for input interruption DAO IOL = 4 mA * CMOS hysteresis input/output * Analog output/CMOS output dual-function pin (CMOS output is not available during analog output.) (Analog output priority: DAE = 1) * Includes input shout down standby control function. IOL = 4mA (Continued) 14 MB90570 Series Type J VCC Circuit Remarks * A/D converter ref+ power supply input pin(AVRH), with power supply protector circuit. P-ch P-ch N-ch N-ch ANE AVR ANE K VCC P-ch N-ch R Hysteresis input Standby control for input interruption Analog input IOL = 4 mA * CMOS hysteresis input /analog input dual-function pin. * CMOS output * Includes input shut down function at input shut down standby. L VCC N-ch N-ch R Hysteresis input IOL = 4 mA Standby control for input interruption * Hysteresis input * N-ch open-drain output * Includes input shut down standby control function. IOL= 4mA 15 MB90570 Series s HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup in the following situations: * When a voltage higher than Vcc or lower than Vss is applied to input or output pins. * When a voltage exceeding the rating is applied between Vcc and Vss. * When AVcc power is supplied prior to the Vcc voltage. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC)and analog input voltages not exceed the digital voltage (VCC). 2. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be more than 2 k 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock MB90570 series X0 Open X1 4. Unused Sub Clock Mode If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin 5. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. 16 MB90570 Series It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. * Using power supply pins VCC VSS VCC VSS VSS MB90570 series VCC VCC VSS VSS VCC 6. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 8. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS. 9. N.C. Pins The N.C. (internally connected) pins must be opened for use. 10. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 V to 2.7 V). 11. Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A) 17 MB90570 Series The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs should not become indeterminate. (MB90F574,MB90F574A,MB90574C) Timing chart of indeterminate outputs from ports 0 and 1 Oscillation setting time *2 Step-down circuit setting time *1 VCC (power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Period of indeterminate *1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time 218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms) 12. Initialization In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again to initialize these registers. 13. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 14. Precautions for Use of 'DIV A, Ri,' and 'DIVW A, Ri' Instructions The signed multiplication-division instructions 'DIV A, Ri,' and 'DIVW A, RWi' should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value '00h.' If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than '00h,' then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 15. Precautions for Use of REALOS Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used. 18 MB90570 Series s BLOCK DIAGRAM Interrupt controller F2MC-16LX CPU Port 7 X0, X1 X0A, X1A RST HST P00/AD00 to P07/AD07 P10/AD08 to P17/AD15 P20/A16 to P27/A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1 8/16-bit PPG timer ch.0 Port 5 2 2 2 SIO x 2 ch 3 P70 to P72 P73/DA0 P74/DA1 DVCC DVSS Main clock Sub clock Clock control block (including timebase timer) 8-bit D/A converter x 2 ch. 2 8 8 8 8 Port 0, 1, 2 16 Port 9 Chip select output 8 8 P90/CS0 to P97/CS7 Port A 2 6 External bus interface 8/16-bit up/down counter/timer PA1/BIN0 PA2/ZIN0 6 PA3/AIN1/IRQ7 PA4/BIN1 PA5/ZIN1 2 PA6/SDA PA7/SCL DTP/ external interrupt circuit x 8 ch. PA0/AIN0/IRQ6 6 6 Port 3 Port 4 2 2 2 UART0 (SCI), UART1 (SCI) Internal data bus I2C bus PB0/IRQ0 to PB5/IRQ5 Port B PB7 PB6/ADTG P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3 P56/IN0 P57/IN1 2 8/10-bit A/D converter x 8 ch. 8 8 AVRL AVRH AVCC AVSS P80/AN0 to P87/AN7 Port 8 Port C 4 PC0 to PC3 Input capture (ICU) 16-bit free run timer P64/OUT0 to P67/OUT3 P60/SIN4 P61/SOT4 P62/SCK4 Port 6 P63/CKOT Clock output SIO x 1 ch. 4 4 Output compare (OCU) RAM ROM Other pins MD0 to MD2, C, VCC, VSS P00 to P07 (8 ports): Provided with a register optional input pull-up resistor P10 to P17 (8 ports): Provided with a register optional input pull-up resistor P40 to P47 (8 ports): Heavy-current (IOL = 10 mA) port P60 to P67 (8 ports): Provided with a register optional input pull-up resistor 19 MB90570 Series s MEMORY MAP Single chip mode A mirror function is supported. FFFFFFH ROM area Address #1 FC0000H 010000H ROM area (image of Address #2 bank FF) 004000H Address #3 RAM Register 000100H 0000C0H 000000H Peripheral Internal ROM external bus mode A mirror function is supported. ROM area External ROM external bus mode ROM area (image of bank FF) RAM Register Peripheral RAM Register Peripheral Part number MB90573 MB90574/C MB90F574/A Address #1* FE0000H FC0000H FC0000H Address #2 * 004000H 004000H 004000H Address #3 * 001800H 002900H 002900H : Internal access memory : External access memory : Inhibited area *: Addresses #1, #2 and #3 are unique to the product type. Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. 20 MB90570 Series s F2MC-16LX CPU PROGRAMMING MODEL * Dedicated registers AH AL : Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. DPR : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional data space. USP SSP PS PC PCB DTB USB SSB ADB 8-bit 16-bit 32-bit 21 MB90570 Series * General-purpose registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180H + (RP x 10H) RW0 16-bit * Processor status (PS) ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value -- : Reserved X : Undefined ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0 22 MB90570 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H SMR0 SCR0 Serial mode register 0 Serial control register 0 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA DDRB DDRC ODR4 ADER Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port B direction register Port C direction register Port 4 output pin register Analog input enable register Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Port C data register Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W UART0 (SCI) 00000000B 00000100B Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port 4 Port 8, 8/10-bit A/D converter 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ---00000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 23 MB90570 Series Address 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH to 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H Abbreviated register name SIDR0/ SODR0 SSR0 SMR1 SCR1 SIDR1/ SODR1 SSR1 CDCR0 Register name Serial input data register 0/ serial output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Serial input data register 1/ serial output data register 1 Serial status register 1 Communications prescaler control register 0 Read/ write R/W R/W R/W R/W R/W R/W R/W Resource name UART0 (SCI) Initial value XXXXXXXXB 00001-00B 00000000B 00000100B XXXXXXXXB 00001-00B UART1 (SCI) Communications prescaler register 0 Communications prescaler register 0 0---1111B (Disabled) CDCR1 Communications prescaler control register 1 R/W 0---1111B (Disabled) ENIR EIRR ELVR DTP/interrupt enable register DTP/interrupt factor register Request level setting register (Disabled) ADCS1 ADCS2 ADCR1 ADCR2 DADR0 DADR1 DACR0 DACR1 CLKR A/D control status register lower digits A/D control status register upper digits A/D data register lower digits A/D data register upper digits D/A converter data register ch.0 D/A converter data register ch.1 D/A control register 0 D/A control register 1 Clock output enable register (Disabled) PRLL0 PRLH0 PPG0 reload register L ch.0 PPG0 reload register H ch.0 R/W R/W 8/16-bit PPG timer 0 XXXXXXXXB XXXXXXXXB R/W R/W or W R W R/W R/W R/W R/W R/W Clock monitor function 8-bit D/A converter 8/10-bit A/D converter 00000000B 00000000B XXXXXXXXB 0 0 0 0 1 - XXB XXXXXXXXB XXXXXXXXB -------0B -------0B ----0000B R/W R/W R/W DTP/external interrupt circuit 00000000B XXXXXXXXB 00000000B 00000000B (Continued) 24 MB90570 Series Address 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH Abbreviated register name PRLL1 PRLH1 PPGC0 PPGC1 PPGOE Register name PPG1 reload register L ch.1 PPG1 reload register H ch.1 PPG0 operating mode control register ch.0 PPG1 operating mode control register ch.1 PPG0 and 1 output control registers ch.0 and ch.1 Serial mode control lower status register 0 Serial mode control upper status register 0 Serial data register 0 Serial mode control lower status register 1 Serial mode control upper status register 1 Serial data register 1 Read/ write R/W R/W R/W R/W R/W Resource name 8/16-bit PPG timer 1 8/16-bit PPG timer 0 8/16-bit PPG timer 1 8/16-bit PPG timer 0, 1 Initial value XXXXXXXXB XXXXXXXX B 0 X 0 0 0 XX 1 B 0X000001B 0 0 0 0 0 0XXB (Disabled) SMCSL0 SMCSH0 SDR0 R/W R/W R/W (Disabled) SMCSL1 SMCSH1 SDR1 R/W R/W R/W (Disabled) IPCP0 IPCP1 ICS01 ICU data register ch.0 ICU data register ch.1 ICU control status register R R R/W (Disabled) TCDT TCCS Free run timer data register Free run timer control status register R/W R/W 16-bit I/O timer (16-bit free run timer section) 00000000B 00000000B 00000000B XXXXXXXXB XXXXXXXXB 16-bit I/O timer (output compare (OCU) section) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit I/O timer (input capture (ICU) section) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B Extended I/O serial interface 1 ----0000B 00000010B XXXXXXXXB Extended I/O serial interface 0 ----0000B 00000010B XXXXXXXXB (Disabled) OCCP0 OCCP1 OCCP2 OCU compare register ch.0 OCU compare register ch.1 OCU compare register ch.2 R/W R/W R/W (Continued) 25 MB90570 Series Address 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH Abbreviated register name OCCP3 OCS0 OCS1 OCS2 OCS3 Register name OCU compare register ch.3 OCU control status register ch.0 OCU control status register ch.1 OCU control status register ch.2 OCU control status register ch.3 Read/ write R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB XXXXXXXXB 16-bit I/O timer (output compare (OCU) section) 0000--00B ---00000B 0000--00B ---00000B (Disabled) IBSR IBCR ICCR IADR IDAR I2C bus status register I2C bus control register I2C bus clock control register I C bus address register I C bus data register 2 2 R R/W R/W R/W R/W (Disabled) I2C interface 00000000B 00000000B - - 0 XXXXXB - XXXXXXXB XXXXXXXXB ROMM UDCR0 UDCR1 RCR0 RCR1 CSR0 CCRL0 CCRH0 CSR1 CCRL1 CCRH1 SMCSL2 SMCSH2 SDR2 ROM mirroring function selection register Up/down count register 0 Up/down count register 1 Reload compare register 0 Reload compare register 1 Counter status register 0 W R R W W R/W ROM mirroring function selection module -------1B 00000000B 00000000B 8/16-bit up/down counter/timer 00000000B 00000000B 00000000B -0000000B (Reserved area)* Counter control register 0 Counter status register 1 3 R/W R/W (Reserved area)*3 8/16-bit up/down counter/timer 00000000B 00000000B -0000000B -0000000B ----0000B Counter control register 1 Serial mode control lower status register 2 Serial mode control higher status register 2 Serial data register 2 R/W R/W R/W R/W (Disabled) 8/16-bit up/down counter/timer Extended I/O serial interface 2 00000010B XXXXXXXXB (Continued) 26 MB90570 Series Address 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H to 00008BH 00008CH 00008DH 00008EH 00008FH to 00009DH 00009EH Abbreviated register name CSCR0 CSCR1 CSCR2 CSCR3 CSCR4 CSCR5 CSCR6 Register name Chip selection control register 0 Chip selection control register 1 Chip selection control register 2 Chip selection control register 3 Chip selection control register 4 Chip selection control register 5 Chip selection control register 6 Read/ write R/W R/W R/W R/W R/W R/W R/W Resource name Initial value ----0000B ----0000B ----0000B Chip select output ----0000B ----0000B ----0000B ----0000B (Disabled) RDR0 RDR1 RDR6 Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 6 input pull-up resistor setup register R/W R/W R/W Port 0 Port 1 Port 6 00000000B 00000000B 00000000B (Disabled) Program address detection control status register Delayed interrupt factor generation/ cancellation register Low-power consumption mode control register Clock select register Address match detection function Delayed interrupt generation module Low-power consumption (standby) mode PACSR R/W 00000000B 00009FH DIRR R/W -------0B 0000A0H 0000A1H 0000A2H to 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH LPMCR CKSCR R/W R/W 00011000B 11111100B (Disabled) ARSR HACR ECSR WDTC TBTC WTC Automatic ready function select register Upper address control register Bus control signal select register Watchdog timer control register Timebase timer control register Clock timer control register W W W R/W R/W R/W Watchdog timer Timebase timer Clock timer External bus pin 0011--00B 00000000B 00000000B XXXXXXXX B 1--00100B 1X000000B (Continued) 27 MB90570 Series (Continued) Address 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH 000100H to 000###H 000###H to 001FEFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H to 001FFFH 28 PADR1 PADR0 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 FMCS Flash control register Abbreviated register name Register name Read/ write (Disabled) R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (External area)*1 Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B Flash interface 0 0 0 X 0 XX 0 B Resource name Initial value (RAM area)*2 (Reserved area)*3 Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 R/W R/W R/W R/W R/W R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area) MB90570 Series Descriptions for read/write R/W: Readable and writable R: Read only W: Write only Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. - : This bit is unused. The initial value is undefined. *1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *2: For details of the RAM area, see "s MEMORY MAP". *3: The reserved area is disabled because it is used in the system. Notes: * For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. * The addresses following 0000FFH are reserved. No external bus access signal is generated. * Boundary ####H between the RAM area and the reserved area varies with the product model. 29 MB90570 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source Reset INT9 instruction Exception 8/10-bit A/D converter Input capture 0 (ICU) include DTP0 (external interrupt 0) Input capture 1 (ICU) include Output compare 0 (OCU) match Output compare 1 (OCU) match Output compare 2 (OCU) match Output compare 3 (OCU) match Extended I/O serial interface 0 16-bit free run timer Extended I/O serial interface 1 Clock timer Extended I/O serial interface 2 DTP1 (external interrupt 1) DTP2/DTP3 (external interrupt 2/ external interrupt 3) 8/16-bit PPG timer 0 counter borrow DTP4/DTP5 (external interrupt 4/ external interrupt 5) 8/16-bit PPG timer 1 counter borrow 8/16-bit up/down counter/timer 0 borrow/overflow/inversion 8/16-bit up/down counter/timer 0 compare match 8/16-bit up/down counter/timer 1 borrow/overflow/inversion 8/16-bit up/down counter/timer 1 compare match DTP6 (external interrupt 6) Timebase timer x x x x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H ICR00 FFFFCCH FFFFC8H ICR01 FFFFC4H FFFFC0H ICR02 FFFFBCH FFFFB8H ICR03 FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H ICR06 FFFF9CH FFFF98H ICR07 FFFF94H FFFF90H ICR08 FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H ICR10 FFFF7CH FFFF78H FFFF74H ICR11 0000BAH 0000BBH Low 0000BAH 0000B9H 0000B8H 0000B7H 0000B6H ICR05 0000B5H ICR04 0000B4H 0000B3H 0000B2H 0000B1H 0000B0H Interrupt control register ICR -- -- -- Address -- -- -- Priority High (Continued) 30 MB90570 Series (Continued) Interrupt source DTP7 (external interrupt 7) I2C interface UART1 (SCI) reception complete UART1 (SCI) transmission complete UART0 (SCI) reception complete UART0 (SCI) transmission complete Flash memory Delayed interrupt generation module : Can be used x : Can not be used : Can be used. With EI2OS stop function. x x x EI2OS support Interrupt vector Number # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFF70H FFFF6CH FFFF68H ICR13 FFFF64H FFFF60H ICR14 FFFF5CH FFFF58H FFFF54H ICR15 0000BFH Low 0000BEH 0000BDH Interrupt control register ICR ICR12 Address 0000BCH Priority High 31 MB90570 Series s PERIPHERALS 1. I/O Port (1) Input/output Port Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). 32 MB90570 Series (2) Register Configuration * Port 0 data register (PDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000000H (PDR1) P07 R/W bit 6 P06 R/W bit 11 P13 R/W bit 5 P05 R/W bit 10 P12 R/W bit 4 P04 R/W bit 9 P11 R/W bit 3 P03 R/W bit 2 P02 R/W bit 1 P01 R/W bit 0 P00 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 1 data register (PDR1) Address bit 15 000001H P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P10 R/W (PDR0) * Port 2 data register (PDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000002H (PDR3) P27 R/W bit 6 P26 R/W bit 5 P25 R/W bit 4 P24 R/W bit 3 P23 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Initial value XXXXXXXX B * Port 3 data register (PDR3) Address bit 15 000003H P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 11 P33 R/W bit 10 P32 R/W bit 9 P31 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P30 R/W (PDR2) Initial value XXXXXXXX B * Port 4 data register (PDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000004H (PDR5) P47 R/W bit 6 P46 R/W bit 11 P53 R/W bit 5 P45 R/W bit 10 P52 R/W bit 4 P44 R/W bit 9 P51 R/W bit 3 P43 R/W bit 2 P42 R/W bit 1 P41 R/W bit 0 P40 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 5 data register (PDR5) Address bit 15 000005H P57 R/W bit 14 P56 R/W bit 13 P55 R/W bit 12 P54 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P50 R/W (PDR4) * Port 6 data register (PDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000006H (PDR7) P67 R/W bit 6 P66 R/W bit 5 P65 R/W bit 4 P64 R/W bit 3 P63 R/W bit 2 P62 R/W bit 1 P61 R/W bit 0 P60 R/W Initial value XXXXXXXX B * Port 7 data register (PDR7) Address bit 15 000007H -- -- bit 14 -- -- bit 13 -- -- bit 12 P74 R/W bit 11 P73 R/W bit 10 P72 R/W bit 9 P71 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P70 R/W (PDR6) Initial value - - - XXXXX B * Port 8 data register (PDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000008H (PDR9) P87 R/W bit 6 P86 R/W bit 5 P85 R/W bit 4 P84 R/W bit 3 P83 R/W bit 2 P82 R/W bit 1 P81 R/W bit 0 P80 R/W Initial value XXXXXXXX B (Continued) 33 MB90570 Series * Port 9 data register (PDR9) Address 000009H bit 15 P97 R/W bit 14 P96 R/W bit 13 P95 R/W bit 12 P94 R/W bit 11 P93 R/W bit 6 PA6 R/W bit 6 PB6 R/W bit 6 -- -- bit 6 D06 R/W bit 10 P92 R/W bit 5 PA5 R/W bit 5 PB5 R/W bit 5 -- -- bit 5 D05 R/W bit 9 P91 R/W bit 4 PA4 R/W bit 4 PB4 R/W bit 4 -- -- bit 4 D04 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P90 R/W bit 3 PA3 R/W bit 3 PB3 R/W bit 3 PC3 R/W bit 3 D03 R/W bit 2 PA2 R/W bit 2 PB2 R/W bit 2 PC2 R/W bit 2 D02 R/W bit 1 PA1 R/W bit 1 PB1 R/W bit 1 PC1 R/W bit 1 D01 R/W bit 0 PA0 R/W bit 0 PB0 R/W bit 0 PC0 R/W bit 0 D00 R/W Initial value 00000000 B Initial value XXXXXXXX B (PDR8) Initial value XXXXXXXX B * Port A data register (PDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000AH (PDRB) PA7 R/W Initial value XXXXXXXX B * Port B data register (PDRB) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000BH (PDRA) PB7 R/W Initial value XXXXXXXX B * Port C data register (PDRC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000CH (Disabled) -- -- * Port 0 direction register (DDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000010H (DDR1) D07 R/W * Port 1 direction register (DDR1) Address 000011H bit 15 D17 R/W bit 14 D16 R/W bit 13 D15 R/W bit 12 D14 R/W bit 11 D13 R/W bit 10 D12 R/W bit 9 D11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D10 R/W (DDR0) Initial value 00000000 B * Port 2 direction register (DDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000012H (DDR3) D27 R/W bit 6 D26 R/W bit 5 D25 R/W bit 4 D24 R/W bit 3 D23 R/W bit 2 D22 R/W bit 1 D21 R/W bit 0 D20 R/W Initial value 00000000 B * Port 3 direction register (DDR3) Address 000013H bit 15 D37 R/W bit 14 D36 R/W bit 13 D35 R/W bit 12 D34 R/W bit 11 D33 R/W bit 10 D32 R/W bit 9 D31 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D30 R/W (DDR2) Initial value 00000000 B * Port 4 direction register (DDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000014H (DDR5) D47 R/W bit 6 D46 R/W bit 5 D45 R/W bit 4 D44 R/W bit 3 D43 R/W bit 2 D42 R/W bit 1 D41 R/W bit 0 D40 R/W Initial value 00000000 B (Continued) 34 MB90570 Series * Port 5 direction register (DDR5) Address 000015H bit 15 D57 R/W bit 14 D56 R/W bit 13 D55 R/W bit 12 D54 R/W bit 11 D53 R/W bit 6 D66 R/W bit 10 D52 R/W bit 5 D65 R/W bit 9 D51 R/W bit 4 D64 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D50 R/W bit 3 D63 R/W bit 2 D62 R/W bit 1 D61 R/W bit 0 D60 R/W Initial value 00000000 B (DDR4) Initial value 00000000 B * Port 6 direction register (DDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000016H (DDR7) D67 R/W * Port 7 direction register (DDR7) Address 000017H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 D74 R/W bit 11 D73 R/W bit 10 D72 R/W bit 9 D71 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D70 R/W (DDR6) Initial value - - - 00000 B * Port 8 direction register (DDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000018H (DDR9) D87 R/W bit 6 D86 R/W bit 11 D93 R/W bit 5 D85 R/W bit 10 D92 R/W bit 4 D84 R/W bit 9 D91 R/W bit 3 D83 R/W bit 2 D82 R/W bit 1 D81 R/W bit 0 D80 R/W Initial value 00000000 B Initial value 00000000 B * Port 9 direction register (DDR9) Address bit 15 000019H D97 R/W bit 14 D96 R/W bit 13 D95 R/W bit 12 D94 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D90 R/W (DDR8) * Port A direction register (DDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001AH (DDRB) DA7 R/W bit 6 DA6 R/W bit 5 DA5 R/W bit 4 DA4 R/W bit 3 DA3 R/W bit 2 DA2 R/W bit 1 DA1 R/W bit 0 DA0 R/W Initial value 00000000 B * Port B direction register (DDRB) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001BH (DDRA) DB7 R/W bit 6 DB6 R/W bit 5 DB5 R/W bit 4 DB4 R/W bit 3 DB3 R/W bit 2 DB2 R/W bit 1 DB1 R/W bit 0 DB0 R/W Initial value 00000000 B * Port C direction register (DDRC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001CH (ODR4) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 DC3 R/W bit 2 DC2 R/W bit 1 DC1 R/W bit 0 DC0 R/W Initial value 00000000 B * Port 4 output pin register (ODR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001DH (DDRC) bit 6 bit 5 OD45 R/W bit 4 OD44 R/W bit 3 OD43 R/W bit 2 OD42 R/W bit 1 OD41 R/W bit 0 OD40 R/W Initial value 00000000 B OD47 OD46 R/W R/W * Port 0 input pull-up resistor setup register (RDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008CH (RDR1) RD07 R/W bit 6 RD06 R/W bit 5 RD05 R/W bit 4 RD04 R/W bit 3 RD03 R/W bit 2 RD02 R/W bit 1 RD01 R/W bit 0 RD00 R/W Initial value 00000000 B (Continued) 35 MB90570 Series (Continued) * Port 1 input pull-up resistor setup register (RDR1) Address 00008DH bit 15 RD17 R/W bit 14 RD16 R/W bit 13 RD15 R/W bit 12 RD14 R/W bit 11 RD13 R/W bit 10 RD12 R/W bit 9 RD11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 RD10 R/W (RDR0) Initial value 00000000 B * Port 6 input pull-up resistor setup register (RDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008EH (Disabled) RD67 R/W bit 6 RD66 R/W bit 5 RD65 R/W bit 4 RD64 R/W bit 3 RD63 R/W bit 2 RD62 R/W bit 1 RD61 R/W bit 0 RD60 R/W Initial value 00000000 B * Analog input enable register (ADER) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001EH (Disabled) ADE7 R/W bit 6 bit 5 bit 4 bit 3 bit 2 ADE2 R/W bit 1 ADE1 R/W bit 0 ADE0 R/W Initial value 11111111 B ADE6 ADE5 R/W R/W ADE4 ADE3 R/W R/W R/W : Readable and writable -- : Reserved X : Undefined 36 MB90570 Series (3) Block Diagram * Input/output port PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode N-ch Pin P-ch * Output pin register (ODR) To resource input From resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write N-ch Pin P-ch DDR read ODR (output pin register) ODR latch ODR write Standby control (SPL=1) ODR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode 37 MB90570 Series * Input pull-up resistor setup register (RDR) PDR (port data register) To resource input PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write Standby control (SPL=1) N-ch P-ch Pull-up resistor About 5.0 k (5.0 V) P-ch Pin DDR read RDR latch RDR write RDR (input pull-up resistor setup register) RDR read Standby control: Stop, timebase timer mode and SPL=1 * Analog input enable register (ADER) ADER (analog input enable register) ADER read ADER latch ADER write PDR (port data register) Internal data bus RMW (read-modify-write type instruction) To analog input PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) P-ch Pin N-ch DDR read Standby control: Stop, timebase timer mode and SPL=1 38 MB90570 Series 2. Timebase Timer The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC) bit 7 . . . . . . . . . . . .bit 0 (WDTC) Address 0000A9H bit 15 RESV -- bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 TBOF R/W bit 10 TBR W bit 9 TBC1 R/W bit 8 TBC0 R/W Initial value 1--00100B R/W : Readable and writable W : Write only -- : Unused RESV: Reserved bit (2) Block Diagram To 8/16-bit PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 22 x 2 3 To watchdog timer ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR: MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) Timebase timer interrupt signal #34*2 RESV -- -- TBIE TBOF TBR TBC1 TBC0 OF: Overflow HCLK: Oscillation clock *1: Switch machine clock from oscillation clock to PLL clock *2: Interrupt signal 39 MB90570 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A8H (TBTC) bit 6 bit 5 bit 4 bit 3 SRST R bit 2 WTE W bit 1 WT1 W bit 0 WT0 W PONR STBR WRST ERST R R R R Initial value XXXXXXXX B R : Read only W: Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 2 Watchdog timer CLR and start Overflow Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector CLR 2-bit counter CLR Watchdog timer reset generation circuit To internal reset generation circuit Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 22 ... 4 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK: Oscillation clock 40 MB90570 Series 4. 8/16-bit PPG Timer The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios. The two modules performs the following operation by combining functions. * 8-bit PPG output 2-CH independent operation mode This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG timer output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same output pulses from PPG0 and PPG1 pins. * 8 + 8-bit PPG timer output operation mode In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. * PPG output operation A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an external add-on circuit. 41 MB90570 Series (1) Register Configuration * PPG0 operating mode control register ch.0 (PPGC0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000044H (PPGC1) PEN0 R/W bit 6 -- -- bit 5 PE00 R/W bit 4 PIE0 R/W bit 3 PUF0 R/W bit 2 -- -- bit 1 -- -- bit 0 RESV -- Initial value 0X0 0 0XX1 B * PPG1 operating mode control register ch.1 (PPGC1) Address bit 15 000045H PEN1 R/W bit 14 -- R/W bit 13 PEI0 R/W bit 12 PIE1 R/W bit 11 PUF1 R/W bit 10 MD1 R/W bit 9 MD0 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 RESV R/W (PPGC0) Initial value 0X0 0 0 0 0 1 B * PPG0, 1 output control register ch.0, ch.1(PPGOE) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000046H (Disabled) bit 6 bit 5 PCS0 R/W bit 10 bit 4 bit 3 bit 2 bit 1 -- -- bit 0 -- -- Initial value XXXXXXXX B Initial value 0 0 0 0 0 0XX B PCS2 PCS1 R/W R/W bit 11 PCM2 PCM1 PCM0 R/W bit 9 R/W R/W * PPG0 reload register H ch.0 (PRLH0) Address bit 15 000041H R/W R/W R/W R/W R/W R/W R/W R/W bit 14 bit 13 bit 12 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL0) * PPG1 reload register H ch.1 (PRLH1) Address bit 15 000043H R/W R/W R/W R/W R/W R/W R/W R/W bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL1) Initial value XXXXXXXX B * PPG0 reload register L ch.0 (PRLL0) Address 000040H bit 15 . . . . . . . . . . . . bit 8 bit 7 (PRLH0) R/W R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B * PPG1 reload register L ch.1 (PRLL1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000042H (PRLH1) R/W : Readable and writable -- : Reserved X : Undefined RESV: Reserved bit 42 MB90570 Series (2) Block Diagram * Block diagram of 8/16-bit PPG timer (ch.0) Data bus for "H" digits Data bus for "L" digits PPG0 reload register PRLH0 PRLL0 PEN0 -- PPG0 operating mode control register ch.0 (PPGC0) PE00 PIE0 PUF0 -- -- RESV PPG0 output control register ch.0 (PPGOE0) PCM2 PCM1 PCM0 Temporary buffer (PRLBH0) R S 2 Q Interrupt request #26* Mode control signal Reload register (L/H selector) Count value Re-load Select signal Clear Pulse selector Underflow PPG1 underflow PPG0 underflow (to PPG1) Down counter (PCNT0) CLK Reverse PPG0 output latch PPG output control circuit Count clock selector 3 Pin P46/PPG0 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Select signal * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 43 MB90570 Series * Block diagram of 8/16-bit PPG timer (ch.1) Data bus for "H" digits Data bus for "L" digits PPG1 reload register PRLH1 Operating mode control signal Temporary buffer (PRLBH1) PRLL1 PEN1 -- PPG1 operating mode control register ch.1 (PPGC1) 2 PPG1 output control register ch.1 (PPGOE1) PEI0 PIE1 PUF1 MD1 MD0 RESV PCS2 PCS1 PCS0 R SQ Interrupt request #28* Reload selector (L/H selector) Count value Re-load Underflow Reverse Select signal Clear PPG1 output latch PPG output control circuit Pin P47/PPG1 MD0 Down counter (PCNT1) PPG1 underflow (to PPG0) CLK PPG0 underflow Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Count clock selector Select signal * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 44 MB90570 Series 5. 16-bit I/O timer The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run timer. Input pulse width and external clock periods can, therefore, be measured. * Block Diagram Internal data bus Input capture Dedicated bus 16-bit free run timer Dedicated bus Output compare 45 MB90570 Series (1) 16-bit free run Timer The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and output compare (OCU). * A counter operation clock can be selected from four internal clocks (/4, /16, /32 and /64). * An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0. (Compare match requires mode setup.) * The counter value can be initialized to "0000H" by a reset, software clear or compare match with OCU compare register 0. * Register Configuration * free run timer data register (TCDT) Address 000056H 000057H bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * free run timer control status register (TCCS) Address 000058H bit 15. . . . . . . . . . . . .bit 8 bit 7 (Disabled) RESV R/W R/W : Readable and writable RESV: Reserved bit bit 6 IVF R/W bit 5 IVFE R/W bit 4 bit 3 bit 2 CLR R/W bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 00000000B STOP MODE R/W R/W * Block Diagram Count value output to ICO and OCU free run timer data register (TCDT) OF 16-bit counter CLK STOP CLR Communications prescaler register 2 free run timer control status register (TCCS) RESV IVF IVFE STOP MODE CLR CLK1 CLK0 OCU compare register ch.0 match signal 16-bit free run timer interrupt request #20* : Machine clock frequency OF : Overflow * : Interrupt number 46 Internal data bus MB90570 Series (2) Input Capture (ICU) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin. There are four sets (four channels) of the input capture external pins and ICU data registers, enabling measurements of maximum of four events. * The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measurements of maximum of four events. * A trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free run timer to the ICU data register (IPCP). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths. * Register Configuration * ICU data register ch.0, ch.1 (IPCP0, IPCP1) Address IPCP0(high): 000051H IPCP1(high): 000053H bit 15 CP15 R bit 14 CP14 R bit 13 CP13 R bit 12 CP12 R bit 11 CP11 R bit 10 CP10 R bit 9 CP09 R bit 8 bit 7 . . . . . . . . . . . . . bit 0 CP08 R (IPCP0 low, IPCP1 low) Initial value XXXXXXXXB Address IPCP0(low): 000050H IPCP1(low): 000052H bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 CP06 R bit 5 CP05 R bit 4 CP04 R bit 3 CP03 R bit 2 CP02 R bit 1 CP01 R bit 0 CP00 R Initial value XXXXXXXXB (IPCP0 high, IPCP1 high) CP07 R Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is detected. (You can word-access this register, but you cannot program it.) * ICU control status register (ICS01) Address 000054H bit 15. . . . . . . . . . . . bit 8 (Disabled) bit 7 ICP1 R/W R/W : Readable and writable R : Read only X : Undefined bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 EG11 R/W bit 2 EG10 R/W bit 1 bit 0 Initial value 00000000B EG01 EG00 R/W R/W 47 MB90570 Series * Block Diagram Internal data bus Latch signal Output latch ICU data register (IPCP) Edge detection circuit P56/IN0 Pin P57/IN1 Pin 2 ICU control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Data latch signal IPCP0H 2 IPCP1H IPCP1L IPCP0L 16 16-bit free run timer 16 Interrupt request #12* Interrupt request #14* * : Interrupt number 48 MB90570 Series (3) Output Compare (OCU) The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free run timer. The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit. * Register Configuration * OCU control status register ch.1, ch.3 (OCS1, OCS3) Address 000063H 000065H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 OTD0 R/W Initial value 0000 - - 00 B (OCS0, OCS2) Initial value - - - 00000 B CMOD OTE1 R/W R/W OTE0 OTD1 R/W R/W * OCU control status register ch.0, ch.2 (OCS0, OCS2) Address 000062H 000064H bit 15. . . . . . . . . . . . bit 8 (OCS1, OCS3) bit 7 ICP1 R/W bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 -- -- bit 2 -- -- bit 1 CST1 R/W bit 0 CST0 R/W * OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3) Address OCCP0 (high order address): 00005BH OCCP1 (high order address): 00005DH OCCP2 (high order address): 00005FH OCCP3 (high order address): 000061H bit 15 C15 R/W bit 14 C14 R/W bit 13 C13 R/W bit 12 C12 R/W bit 11 C11 R/W bit 10 C10 R/W bit 9 C09 R/W bit 8 C08 R/W Initial value XXXXXXXXB Address OCCP0 (low order address): 00005AH OCCP1 (low order address): 00005CH OCCP2 (low order address): 00005EH OCCP3 (low order address): 000060H bit 7 C07 R/W bit 6 C06 R/W bit 5 C05 R/W bit 4 C04 R/W bit 3 C03 R/W bit 2 C02 R/W bit 1 C01 R/W bit 0 C00 R/W Initial value XXXXXXXXB R/W : Readable and writable -- : Reserved X : Undefined 49 MB90570 Series * Block diagram #16* OCU control status register ch.0, ch.1 (OCS0, OCS1) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- #15* -- Output compare interrupt request CST1 CST0 2 2 16-bit free run timer Compare control circuit 3 OCCP3 OCU compare register ch.3 Compare control circuit 2 Internal data bus OCCP2 OCU compare register ch.2 Output control circuit 2 Output control circuit 3 P67/OUT3 Pin P66/OUT2 Pin P65/OUT1 Compare control circuit 1 OCCP1 OCU compare register ch.1 P64/OUT0 Compare control circuit 0 OCCP0 OCU compare register ch.0 2 OCU control status register ch.2, ch.3 (OCS2, OCS3) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 Output control circuit 0 Output control circuit 1 Pin Pin 2 ICE0 -- -- CST1 CST0 #18* #17* * : Interrupt number Output compare interrupt request 50 MB90570 Series 6. 8/16-bit up/down counter/timer The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit reload compare registers, and their controllers. (1) Register configuration * Up/down count register 0 (UDCR0) Address 000070H bit 15 . . . . . . . . . . . . bit 8 bit 7 (UDCR1) D07 R bit 6 D06 R bit 11 D13 R bit 6 D06 W bit 11 D13 W bit 6 CITE R/W bit 6 bit 5 D05 R bit 10 D12 R bit 5 D05 W bit 10 D12 W bit 5 UDIE R/W bit 5 bit 4 D04 R bit 9 D11 R bit 4 D04 W bit 9 D11 W bit 4 CMPF R/W bit 4 bit 3 D03 R bit 8 D10 R bit 3 D03 W bit 8 D10 W bit 3 bit 2 bit 1 bit 0 UDF0 R bit 0 Initial value - 0000000 B Initial value 00000000 B bit 2 D02 W bit 1 D01 W bit 0 D00 W Initial value 00000000 B Initial value 00000000 B bit 2 D02 R bit 1 D01 R bit 0 D00 R Initial value 00000000 B Initial value 00000000 B * Up/down count register 1 (UDCR1) Address 000071H bit 15 D17 R Address 000072H bit 14 D16 R bit 13 D15 R bit 12 D14 R bit 7 . . . . . . . . . . . . . bit 0 (UDCR0) * Reload compare register 0 (RCR0) bit 15 . . . . . . . . . . . . bit 8 bit 7 (RCR1) D07 W * Reload compare register 1 (RCR1) Address 000073H bit 15 D17 W Address 000074H 000078H bit 14 D16 W bit 13 D15 W bit 12 D14 W bit 7 . . . . . . . . . . . . . bit 0 (RCR0) * Counter status register 0, 1 (CSR0, CSR1) bit 15 . . . . . . . . . . . . bit 8 bit 7 (Reserved area) CSTR R/W Address 000076H 00007AH bit 15 . . . . . . . . . . . . bit 8 bit 7 (CCRH0, CCRH1) OVFF UDFF UDF1 R/W bit 3 R/W bit 2 R bit 1 * Counter control register 0, 1 (CCRL0, CCRL1) -- -- * Counter control register 0 (CCRH0) Address 000077H bit 15 bit 14 bit 13 CFIE R/W bit 13 CFIE R/W bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL0) Initial value 00000000 B M16E CDCF R/W Address 00007BH bit 15 R/W bit 14 CDCF R/W CLKS CMS1 CMS0 CES1 CES0 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL1) Initial value - 0000000 B CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W R/W R/W R/W R/W * Counter control register 1 (CCRH1) -- -- CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W : Readable and writable R : Read only W : Write only -- : Undefined 51 MB90570 Series (2) Block Diagram * Block diagram of 8/16-bit up/down counter/timer 0 Internal data bus RCR0 Reload compare register 0 Re-load control circuit UDCR0 Up/down count register 0 Counter control register 0 (CCRL0) CARRY/ BORRW (to channel 1) -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow PA2/ZIN0 Pin Edge/level detection circuit Counter clear circuit Compare control circuit PA0/AIN0/IRQ6 Pin Pin PA1/BIN0 Prescaler Count clock Counter status register 0 (CSR0) UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #29* Interrupt request #30* M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 0 (CCRH0) M16E (to channel 1) * : Interrupt number : Machine clock frequency 52 MB90570 Series * Block diagram of 8/16-bit up/down counter/timer 1 Internal data bus RCR1 Reload compare register 1 Re-load control circuit Up/down count register 1 Counter control register 1 (CCRL1) UDCR1 -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow PA5/ZIN1 Pin Edge/level detection circuit Counter clear circuit Compare control circuit CARRY/BORRW (from channel 0) PA3/AIN1/IRQ7 Pin Pin PA4/BIN1 M16E (from channel 1) Prescaler Count clock Counter status register 1 (CSR1) UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #31* Interrupt request #32* -- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 1 (CCRH1) * : Interrupt number : Machine clock frequency 53 MB90570 Series 7. Extended I/O serial interface The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. For data transfer, you can select LSB first/MSB first. (1) Register Configuration * Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2) Address SMCSH0: 000049H SMCSH1: 00004DH SMCSH2: 00007DH bit 15 bit 14 bit 13 bit 12 SIE R/W bit 11 SIR R/W bit 6 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (SMCSL) Initial value 00000010 B SMD2 SMD1 SMD0 R/W R/W R/W BUSY STOP STRT R bit 5 R/W bit 4 R/W bit 3 MODE R/W bit 3 D3 R/W bit 2 BDS R/W bit 2 D2 R/W bit 1 SOE R/W bit 1 D1 R/W bit 0 SCOE R/W bit 0 D0 R/W Initial value XXXXXXXX B Initial value - - - - 0000 B * Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2) Address SMCSL0: 000048H SMCSL1: 00004CH SMCSL2: 00007CH bit 15 . . . . . . . . . . . . bit 8 bit 7 (SMCSH) -- -- -- -- * Serial data register 0 to 2 (SDR0 to SDR2) Address SDR0: 00004AH SDR1: 00004EH SDR2: 00007EH bit 15 . . . . . . . . . . . . bit 8 bit 7 (Disabled) D7 R/W bit 6 D6 R/W -- -- bit 5 D5 R/W -- -- bit 4 D4 R/W R/W : Readable and writable R : Read only -- : Reserved X : Undefined 54 MB90570 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 Pin P40/SIN0 Pin P43/SIN1 Pin P50/SIN2 Serial data register (SDR) Transfer direction selection Read Write Pin P41/SOT0 Pin P44/SOT1 Pin Pin P45/SCK1 Pin P52/SCK2 Pin P42/SCK0 Internal clock Control circuit P51/SOT2 Shift clock counter D7 to D0 (LSB first) 2 1 0 SIE SIR BUSY STOP STRT SMD2 SMD1 SMD0 -- -- -- -- MODE BDS SOE SCOE Serial mode control status register (SMCS) *: Interrupt number Interrupt request #19 (SMCS0)* #21 (SMCS1)* #23 (SMCS2)* 55 MB90570 Series 8. I2C Interface The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus. The MB90570/A series contains one channel of an I2C interface, having the following features. * * * * * * * Master/slave transmission/reception Arbitration function Clock synchronization function Slave address/general call address detection function Transmission direction detection function Repeated generation function start condition and detection function Bus error detection function (1) Register Configuration * I2C bus status register (IBSR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000068H (IBCR) BB R bit 6 RSC R bit 5 AL R bit 4 LRB R bit 3 TRX R bit 2 AAS R bit 1 GCA R bit 0 FBT R Initial value 00000000B * I2C bus control register (IBCR) Address 000069H bit 15 BER R/W bit 14 BEIE R/W bit 13 SCC R/W bit 12 MSS R/W bit 11 ACK R/W bit 10 GCAA R/W bit 9 INTE R/W bit 8 INT R/W bit 7 . . . . . . . . . . . . bit 0 (IBSR) Initial value 00000000B * I2C bus clock control register (ICCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006AH (IADR) -- -- bit 6 -- -- bit 5 EN R/W bit 4 CS4 R/W bit 3 CS3 R/W bit 2 CS2 R/W bit 1 CS1 R/W bit 0 CS0 R/W Initial value --0XXXXXB * I2C bus address register (IADR) Address 00006BH bit 15 -- -- bit 14 A6 R/W bit 13 A5 R/W bit 12 A4 R/W bit 11 A3 R/W bit 10 A2 R/W bit 9 A1 R/W bit 8 A0 R/W bit 7 . . . . . . . . . . . . bit 0 (ICCR) Initial value -XXXXXXXB * I2C bus data register (IDAR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006CH (Disabled) D7 R/W bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value XXXXXXXXB R/W : Readable and writable R : Read only -- : Reserved X : Indeterminate 56 MB90570 Series (2) Block Diagram Internal data bus I2C bus control register (IBCR) I2C bus status register (IBSR) BB RSC AL LRB TRX AAS GCA FBT Transmission complete flag Transmit/receive Detection of first byte Interrupt request signal #36* SDA line SCL line I2C enable Pin IDAR register Arbitration lost detection circuit PA7/SCL Pin PA6/SDA Repeat start General call BER BEIE SCC MSS ACK GCAA INTE INT GC-ACK enable Interrupt enable ACK enable Master Error Start Bus busy Last bit Number of interrupt request generated Start stop condition generation circuit Start stop condition detection circuit Slave address comparison circuit IADR register Clock control block Sync Clock divider 1 4 (1/5 to 1/8) Count clock selector 1 Clock divider 2 8 Count clock selector 2 Shift clock generation circuit I2C enable -- -- EN CS4 CS3 CS2 CS1 CS0 I2C bus clock control register (ICCR) : Machine clock frequency * : Interrupt number Slave 57 MB90570 Series 9. UART0 (SCI), UART1 (SCI) UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing synchronous or asynchronous communication (start-stop synchronization system). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: Embedded dedicated baud rate generator External clock input possible Internal clock (a clock supplied from 16-bit reload timer 0 can be used.) Internal machine clock Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps For 6 MHz, 8 MHz, 10 MHz CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps 12 MHz and 16 MHz * Data length: 7 bit to 9 bit selective (without a parity bit) 6 bit to 8 bit selective (with a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) * Interrupt request: Receive interrupt (receive complete, receive error detection) Transmit interrupt (transmission complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) } 58 MB90570 Series (1) Register Configuration * Serial control register 0,1 (SCR0, SCR1) Address 000021H 000025H bit 15 PEN R/W bit 14 P R/W bit 13 SBL R/W bit 12 CL R/W bit 7 MD1 R/W bit 11 A/D R/W bit 6 MD0 R/W bit 11 bit 10 REC W bit 5 CS2 R/W bit 10 -- -- bit 5 D5 R bit 5 D5 W bit 5 -- -- bit 9 RXE R/W bit 4 CS1 R/W bit 9 RIE R/W bit 4 D4 R bit 4 D4 W bit 4 -- -- bit 8 TXE R/W bit 3 CS0 R/W bit 8 TIE R/W bit 3 D3 R bit 3 D3 W bit 3 DIV3 R/W bit 2 D2 R bit 2 D2 W bit 2 DIV2 R/W bit 1 D1 R bit 1 D1 W bit 1 DIV1 R/W bit 0 D0 R bit 0 D0 W bit 0 DIV0 R/W bit 2 RESV R/W bit 1 SCKE R/W bit 0 SOE R/W bit 7 . . . . . . . . . . . . . bit 0 (SMR0, SMR1) Initial value 00000100 B * Serial mode register 0, 1 (SMR0, SMR1) Address 000020H 000024H bit 15. . . . . . . . . . . . bit 8 (SCR0, SCR1) Initial value 00000000 B * Serial status register 0,1 (SSR0, SSR1) Address 000023H 000027H bit 15 PE R bit 14 ORE R bit 13 FRE R bit 12 bit 7 . . . . . . . . . . . . . bit 0 (SIDR0, SIDR1/SODR0,SODR1) RDRF TRDE R bit 7 D7 R R bit 6 D6 R bit 6 D6 W bit 6 -- -- Initial value 00001 - 00 B * Serial input data register 0,1 (SIDR0, SIDR1) Address 000022H 000026H bit 15. . . . . . . . . . . . bit 8 (SSR0, SSR1) Initial value XXXXXXXX B * Serial output data register 0,1 (SODR0, SODR1) Address 000022H 000026H bit 15. . . . . . . . . . . . bit 8 (SSR0, SSR1) bit 7 D7 W Address 000028H 00002AH bit 15. . . . . . . . . . . . bit 8 (Disabled) bit 7 MD R/W Initial value XXXXXXXX B * Communications prescaler control register 0,1 (CDCR0, CDCR1) Initial value 0 - - - 1111 B R/W: Readable and writable R : Read only W : Write only -- : Reserved X : Undefined RESV: Reserved bit 59 MB90570 Series (2) Block Diagram * UART0 (SCI) Control bus Receive interrupt signal #39* Transmit interrupt signal #40* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P41/SOT0 Dedicated baud rate generator 8/16-bit PPG timer 1 (upper) External clock Pin P42/SCK0 Start bit detection circuit Receive bit counter Receive parity counter Clock selector Transmit clock Receive clock Receive control circuit Pin P40/SIN0 Shift register for reception Reception complete Shift register for transmission SIDR0 Receive condition decision circuit SODR0 Start transmission To I2C reception error generation signal (to CPU) Internal data bus SMR0 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0 register PEN P SBL CL A/D REC RXE TXE SSR0 register PE ORE FRE RDRF TDRE RIE TIE * : Interrupt number 60 MB90570 Series * UART1 (SCI) Control bus Receive interrupt signal #37* Transmit interrupt signal #38* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P44/SOT1 Dedicated baud rate generator 8/16-bit PPG timer 1 (upper) Pin P45/SCK1 Start bit detection circuit Receive bit counter Receive parity counter Clock selector Transmit clock Receive clock Receive control circuit Pin P43/SIN1 Shift register for reception Reception complete Shift register for transmission SIDR1 Receive condition decision circuit SODR1 Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus SMR1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR1 register PEN P SBL CL A/D REC RXE TXE SSR1 register PE ORE FRE RDRF TDRE RIE TIE * : Interrupt number 61 MB90570 Series 10. DTP/External Interrupt Circuit DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing. As request levels for IRQ2 to IRQ7, two types of "H" and "L" can be selected for the intelligent I/O service. Rising and falling edges as well as "H" and "L" can be selected for an external interrupt request. For IRQ0 and IRQ1, a request by a level cannot be entered, but both edges can be entered. * : The external peripheral circuit is connected outside the MB90570/A series device. Note: IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt. (1) Register Configuration * DTP/interrupt factor register (EIRR) Address bit 15 000031H ER7 R/W bit 14 ER6 R/W bit 13 ER5 R/W bit 12 ER4 R/W bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 ER0 R/W (ENIR) Initial value XXXXXXXX B * DTP/interrupt enable register (ENIR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000030H (EIRR) EN7 R/W bit 6 EN6 R/W bit 5 EN5 R/W bit 4 EN4 R/W bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W Initial value 00000000 B * Request level setting register (ELVR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 Low order address 000032H (ELVR upper) LB3 R/W Address bit 15 High order address 000033H LB7 R/W bit 14 LA7 R/W bit 13 LB6 R/W bit 12 LA6 R/W bit 6 LA3 R/W bit 11 LB5 R/W bit 5 LB2 R/W bit 10 LA5 R/W bit 4 LA2 R/W bit 9 LB4 R/W bit 3 LB1 R/W bit 2 LA1 R/W bit 1 LB0 R/W bit 0 LA0 R/W Initial value 00000000 B Initial value 00000000 B bit 8 bit 7 . . . . . . . . . . . . bit 0 LA4 R/W (ELVR lower) R/W: Readable and writable X : Undefined 62 Request level setting register (ELVR) LB7 2 2 2 2 2 2 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Level edge selector 7 Level edge selector 5 Level edge selector 3 2 Level edge selector 1 2 (2) Block Diagram PA3/AIN1/IRQ7 Pin Level edge selector 6 Level edge selector 4 Level edge selector 2 Level edge selector 0 PA0/AIN0/IRQ6 Pin PB5/IRQ5 DTP/external interrupt input detection circuit Pin MB90570 Series *: Interrupt number Internal data bus ER7 ER6 ER5 ER4 ER3 ER2 ER1 #35* #33* #27* #25* #24* #13* EN7 EN6 EN5 EN4 EN3 EN2 EN1 PB4/IRQ4 ER0 DTP/interrupt factor register (EIRR) Interrupt request signal Pin PB3/IRQ3 Pin PB2/IRQ2 Pin PB1/IRQ1 Pin PB0/IRQ0 EN0 DTP/interrupt enable register (ENIR) 63 MB90570 Series 11. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 R0 R/W (PACSR) Initial value - - - - - - -0B Note: Upon a reset, an interrupt is canceled. R/W: Readable and writable -- : Reserved The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this register with "1" generates a delay interrupt request. Programming this register with "0" cancels a delay interrupt request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either "0" or "1". For future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) Block Diagram Internal data bus -- -- -- -- -- -- -- R0 Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt number S factor R latch Interrupt request signal #42* 64 MB90570 Series 12. 8/10-bit A/D Converter The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * Minimum conversion time: 26.3 s (at machine clock of 16 MHz, including sampling time) * Minimum sampling time: 4 s/256 s (at machine clock of 16 MHz) * Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below 8 MHz.) * Conversion method: RC successive approximation method with a sample and hold circuit. * 8-bit or 10-bit resolution * Analog input pins: Selectable from eight channels by software Single conversion mode: Selects and converts one channel. Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed. Continuous conversion mode: Repeatedly converts specified channels. Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously.) * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling efficient continuous processing. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selected from software activation, and external trigger (falling edge). 65 MB90570 Series (1) Register Configuration * A/D control status register upper digits (ADCS2) Address 000037H bit 15 BUSY R/W bit 14 INT R/W bit 13 INTE R/W bit 12 PAUS R/W bit 11 STS1 R/W bit 10 STS0 R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (ADCS1) STRT RESV W R/W Initial value 00000000 B * A/D control status register lower digits (ADCS1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000036H (ADCS2) MD1 R/W bit 6 MD0 R/W bit 5 ANS2 R/W bit 4 ANS1 R/W bit 3 ANS0 R/W bit 2 ANE2 R/W bit 1 ANE1 R/W bit 0 ANE0 R/W Initial value 00000000 B * A/D data register upper digits (ADCR2) Address 000039H bit 15 DSEL W bit 14 ST1 W bit 13 ST0 W bit 12 CT1 W bit 11 XCT0 W bit 10 -- -- bit 9 D9 -- bit 8 bit 7 . . . . . . . . . . . . bit 0 D8 -- (ADCR1) Initial value 0 0 0 0 1 - XX B * A/D data register lower digits (ADCR1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000038H (ADCR2) D7 R R/W: Readable and writable R : Read only W : Write only -- : Reserved X : Undefined RESV: Reserved bit bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXX B 66 MB90570 Series (2) Block Diagram A/D control status register (ADCS) Interrupt request #11* BUSY INT INTE PAUS STS1 STS0 STRT DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 PB6/ADTG TO 2 Clock selector Decoder Comparator P87/AN7 P86/AN6 P85/AN5 P84/AN4 P83/AN3 P82/AN2 P81/AN1 P80/AN0 Sample hold circuit Analog channel selector AVRH, AVRL AVCC AVSS 8-bit D/A converter Control circuit A/D data register RESV ST1 ST0 CT1 CT0 (ADCR) -- D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Machine clock frequency TO : 8/16-bit PPG timer channel 1 output * : Interrupt number Internal data bus 67 MB90570 Series 13. 8-bit D/A Converter The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A converter data register ch.0 (DADR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003AH (DADR1) DA07 R/W bit 6 DA06 R/W bit 5 DA05 R/W bit 4 DA04 R/W bit 3 DA03 R/W bit 2 DA02 R/W bit 1 DA01 R/W bit 0 DA00 R/W Initial value XXXXXXXX B * D/A converter data register ch.1 (DADR1) Address 00003BH bit 15 DA17 R/W bit 14 DA16 R/W bit 13 DA15 R/W bit 12 DA14 R/W bit 11 DA13 R/W bit 10 DA12 R/W bit 9 DA11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 DA10 R/W (DADR0) Initial value XXXXXXXX B * D/A control register 0 (DACR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003CH (DACR1) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 -- -- bit 2 -- -- bit 1 -- -- bit 0 DAE0 R/W Initial value - - - - - - -0B * D/A control register 1 (DACR1) Address 00003DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 DAE1 R/W (DACR0) Initial value - - - - - - -0B R/W: Readable and writable -- : Reserved X : Undefined 68 MB90570 Series (2) Block Diagram Internal data bus D/A converter data register ch.1 (DADR1) DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 D/A converter 1 DVRH DA17 D/A converter data register ch.0 (DADR0) DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter 0 DVRL DA07 Pin Pin 2R DA06 2R DA05 2R DA04 2R DA03 2R DA02 2R DA01 2R DA00 2R R P73/DA0 2R DA16 2R DA15 2R DA14 2R DA13 2R DA12 2R DA11 2R DA10 2R R P74/DA1 R R R R R R R R R R R R 2R 2R DVSS Standby control DVSS Standby control D/A control register 1 (DACR1) -- -- -- -- -- -- -- DAE1 D/A control register 0 (DACR0) -- -- -- -- -- -- -- DAE0 Internal data bus 69 MB90570 Series 14. Clock Timer The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt. (1) Register Configuration * Clock timer control register (WTC) . . . . . . . . . . . . bit 8 bit 7 Address bit 15 0000AAH (Disabled) WDCS R/W R/W: Readable and writable R : Read only X : Undefined bit 6 SCE R bit 5 bit 4 bit 3 WTR R/W bit 2 bit 1 bit 0 Initial value 1X0 0 0 0 0 0 B WTIE WTOF R/W R/W WTC2 WTC1 WTC0 R R/W R/W (2) Block Diagram To watchdog timer Clock counter LCLK x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 OF OF OF OF OF OF OF Power-on reset Shift to a hardware standby Shift to stop mode Interval timer selector Counter clear circuit To sub-clock oscillation stabilization time controller Clock timer interrupt request #22* WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clock timer control register (WTC) * : Interrupt number OF : Overflow LCLK : Oscillation sub-clock frequency 70 MB90570 Series 15. Chip Select Output This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip select output pins. When access to an address is detected with a hardware-set area set for each pin register, a select signal is output from the pin. (1) Register Configuration * Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7) Address CSCR1: 000081H CSCR3: 000083H CSCR5: 000085H CSCR7: 000087H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 ACTL R/W bit 6 -- -- bit 10 OPEL R/W bit 5 -- -- bit 9 CSA1 R/W bit 4 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 CSA0 R/W bit 3 ACTL R/W bit 2 OPEL R/W bit 1 CSA1 R/W bit 0 CSA0 R/W (CSCR0, CSCR2, CSCR4, CSCR6) Initial value - - - - 0000 B * Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 CSCR0: 000080H CSCR2: 000082H (CSCR1, CSCR3, CSCR5, CSCR7) -- CSCR4: 000084H -- CSCR6: 000086H R/W: Readable and writable -- : Reserved Initial value - - - - 0000 B 71 MB90570 Series (2) Block Diagram From address (CPU) A23 A22 A17 A16 A15 A14 A01 A00 Address decoder Decode signal Program area Decode 2 Select and set Chip selection control register 0 (CSCR0) Select and set Chip selection control register 1 (CSCR1) Select and set Chip selection control register 2 (CSCR2) Select and set Chip selection control register 3 (CSCR3) Select and set Chip selection control register 4 (CSCR4) Select and set Chip selection control register 5 (CSCR5) Select and set Chip selection control register 6 (CSCR6) Select and set Address decoder P90/CS0 (Program ROM area application) Selector Selector P91/CS1 Selector P92/CS2 Selector P93/CS3 Selector P94/CS4 Selector P95/CS5 Selector P96/CS6 Chip selection control register 7 (CSCR7) Selector P97/CS7 72 MB90570 Series (3) Decode Address Spaces Pin name CSA 1 0 CS0 0 1 1 0 CS1 0 1 1 0 CS2 0 1 1 0 CS3 0 1 1 0 CS4 0 1 1 0 CS5 0 1 1 0 CS6 0 1 1 CS7 -- 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- Decode space F00000H to FFFFFFH F80000H to FFFFFFH FE0000H to FFFFFFH -- E00000H to EFFFFFH F00000H to F7FFFFH FC0000H to FDFFFFH 68FF80H to 68FFFFH 003000H to 003FFFH FA0000H to FBFFFFH 68FF80H to 68FFFFH 68FF00H to 68FF7FH F80000H to F9FFFFH 68FF00H to 68FF7FH 68FE80H to 68FEFFH -- 002800H to 002FFFH 68FE80H to 68FEFFH -- -- 68FF80H to 68FFFFH -- -- -- 68FF00H to 68FF7FH -- -- -- -- Number of area bytes 1 Mbyte 512 kbyte 128 kbyte Disabled 1 Mbyte 512 kbyte 128 kbyte 128 byte 4 kbyte 128 kbyte 128 byte 128 byte 128 kbyte 128 byte 128 byte Disabled 2 kbyte 128 byte Disabled Disabled 128 byte Disabled Disabled Disabled 128 byte Disabled Disabled Disabled Disabled Disabled Adapted to the data ROM and RAM areas, and external circuit connection applications. Adapted to the data ROM and RAM areas, and external circuit connection applications. Adapted to the data ROM and RAM areas, and external circuit connection applications. Adapted to the data ROM and RAM areas, and external circuit connection applications. Adapted to the data ROM and RAM areas, and external circuit connection applications. Adapted to the data ROM and RAM areas, and external circuit connection applications. Remarks Becomes active when the program ROM area or the program vector is fetched. 73 MB90570 Series 16. Communications Prescaler Register This register controls machine clock division. Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O serial interface. The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) Register Configuration * Communications prescaler control register 0,1 (CDCR0, CDCR1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000028H 00002AH (Disabled) MD R/W R/W: Readable and writable -- : Reserved bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 DIV3 R/W bit 2 DIV2 R/W bit 1 DIV1 R/W bit 0 DIV0 R/W Initial value 0 - - - 1111 B 74 MB90570 Series 17. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration * Program address detection register 0 to 2 (PADR0) Address PADR0 (Low order address): 001FF0H R/W Address PADR0 (Middle order address): 001FF1H R/W Address PADR0 (High order address): 001FF2H R/W Address PADR1 (Low order address): 001FF3H R/W Address PADR1 (Middle order address): 001FF4H R/W Address PADR1 (High order address): 001FF5H R/W Address 00009EH bit 7 RESV R/W R/W: Readable and writable X : Undefined RESV: Reserved bit R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 AD0E R/W R/W bit 0 RESV R/W Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B * Program address detection register 3 to 5 (PADR1) * Program address detection control status register (PACSR) RESV RESV R/W R/W RESV AD1E RESV R/W R/W R/W 75 MB90570 Series (2) Block Diagram Internal data bus Address detection register Compare Address latch INT9 instruction F2MC-16LX CPU core Enable bit 76 MB90570 Series 18. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register Configuration * ROM mirroring function selection register (ROMM) Address 00006FH bit 15 -- -- W : Write only -- : Reserved bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 MI W (Disabled) Initial value - - - - - - -1B Note: Do not access this register during operation at addresses 004000H to 00FFFFH. (2) Block Diagram ROM mirroring function selection register (ROMM) Internal data bus Address area Address FF bank 00 bank Data ROM 77 MB90570 Series 19. Low-power Consumption (Standby) Mode The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock (HCLK). Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscillation clock (HCLK). The PLL multiplication circuits stops in the main clock mode. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high-speed. * Hardware standby mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes, modes other than the PLL clock mode are power consumption modes. (1) Register Configuration * Clock select register (CKSCR) Address 0000A1H bit 15 SCM R bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 SCS R/W bit 6 SLP W bit 10 MCS R/W bit 5 SPL R/W bit 9 CS1 R/W bit 4 RST W bit 8 bit 7 . . . . . . . . . . . . bit 0 CS0 R/W bit 3 TMD R/W bit 2 CG1 W bit 1 CG0 R/W bit 0 SSR R/W (LPMCR) Initial value 11111100 B * Low-power consumption mode control register (LPMCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A0H (CKSCR) STP W R/W: Readable and writable R : Read only W : Write only Initial value 00011000 B 78 MB90570 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 SSR CPU intermittent operation cycle selector 2 CPU clock control circuit CPU operation clock Clock mode Sleep signal Stop signal Hardware standby Peripheral clock control circuit S R S R Q Q S R S R Q Q Machine clock Peripheral function operation clock Reset Interrupt Clock selector 2 Oscillation stabilization time selector 2 PLL multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) X0 X1 Pin Pin Clock oscillator Oscillation clock 1/2 Main clock 1/2048 1/4 1/4 1/8 Timebase timer To watchdog timer X0A Pin X1A Pin Oscillation sub-clock Sub-clock oscillator 1/1024 Clock timer 1/8 1/2 1/2 S: Set R: Reset Q: Output 79 MB90570 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVRH Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOHAV Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Power consumption PD Operating temperature Storage temperature *1: *2: *3: *4: *5: TA Tstg -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 15 4 100 50 -15 -4 -100 -50 300 500 800 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW mW mW C C *5 MB90573/4 MB90V570/A MB90574C MB90F574/A *5 *3 *4 *1 *1 *1 *2 *2 *3 *4 Remarks "H" level total maximum output current IOH AVCC, AVRH, AVRL, and DVRH shall never exceed VCC. AVRL shall never exceed AVRH. VI and VO shall never exceed VCC + 0.3 V. The maximum output current is a peak value for a corresponding pin. Average output current is an average current value observed for a 100 ms period for a corresponding pin. Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note: Average output current = operating x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 80 MB90570 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage VCC VCC Smoothing capacitor Operating temperature CS TA Value Min. 3.0 4.5 3.0 0.1 -40 Max. 5.5 5.5 5.5 1.0 +85 Unit V V V F C Remarks Normal operation (MB90574/C) Normal operation (MB90F574/A) Retains status at the time of operation stop * * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C pin connection circuit C CS 81 MB90570 Series 3. DC Characteristics (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- -- -- -- -- VCC + 0.3 VCC + 0.3 0.2 VCC VSS + 0.3 -- V V V V V Parameter Symbol "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Pin name VIHS VIHM VILS VILM VOH CMOS hysteresis input 0.8 VCC pin VCC = 3.0 V to 5.5 V (MB90573) MD pin input VCC - 0.3 (MB90574) CMOS VCC = 4.5 V to 5.5 V hysteresis input (MB90F574) VSS - 0.3 pin MD pin input Other than PA6 VCC = 4.5 V and PA7 IOH = -2.0 mA All output pins VCC = 4.5 V IOL = 2.0 mA VSS - 0.3 VCC - 0.5 VOL -- -- 0.4 V Open-drain output Ileak leakage current Input leakage current Pull-up resistance Pull-down resistance IIL PA6, PA7 -- -- 0.1 5 A Other than PA6 VCC = 5.5 V and PA7 VSS < VI < VCC P00 to P07, P10 to P17, P60 to P67, RST, MD0, MD1 MD0 to MD2 VCC VCC VCC VCC VCC VCC VCC VCC VCC -5 -- 5 A RUP -- 15 30 100 k RDOWN ICC ICC ICC ICC -- Internal operation at 16 MHz VCC at 5.0 V Normal operation Internal operation at 16 MHz VCC at 5.0 V A/D converter operation Internal operation at 16 MHz VCC at 5.0 V D/A converter operation 15 -- -- -- -- -- -- -- -- -- 30 30 85 50 35 90 55 40 95 65 100 40 130 80 45 140 85 50 145 85 k mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C Power supply current* ICC ICC ICC ICC ICC (Continued) 82 MB90570 Series (Continued) Parameter Symbol Pin name (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. When data written in flash mode programming of erasing Internal operation at 16 MHz VCC = 5.0 V In sleep mode Internal operation at 8 kHz VCC = 5.0 V TA = +25C Subsystem operation Internal operation at 8 kHz VCC = 5.0 V TA = +25C In subsleep mode Internal operation at 8 kHz VCC = 5.0 V TA = +25C In clock mode TA = +25C In stop mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 95 7 5 15 0.1 4 0.03 30 0.1 10 15 30 1.0 5 0.1 10 140 12 10 20 1.0 7 1 50 1 50 30 50 30 20 10 80 mA MB90F574/A mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A A A A A A A pF MB90574C MB90574 MB90F574/A MB90574C MB90574 MB90F574/A MB90574C ICC ICCS ICCS ICCS ICCL ICCL Power supply current* ICCL ICCLS ICCLS ICCLS ICCT ICCT ICCT ICCH ICCH Input CIN capacitance VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Other than AVCC, AVSS, VCC, VSS * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. 83 MB90570 Series 4. AC Characteristics (1) Reset, Hardware Standby Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRSTL tHSTL RST HST -- 4 tCP* 4 tCP* -- -- ns ns Parameter Reset input time Hardware standby input time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC characteristics Pin CL CL is a load capacitance connected to a pin under test. Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins. 84 MB90570 Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. 0.05 30 ms * Due to repeated 4 -- ms operations Parameter Power supply rising time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC VCC -- * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers. tR VCC 2.7 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 0.2 V 3.0 V VSS It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 85 MB90570 Series (3) Clock Timings (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Typ. Max. FC X0, X1 3 -- 16 MHz Clock frequency FCL X0A, X1A -- 32.768 -- kHz tHCYL X0, X1 62.5 -- 333 ns Clock cycle time tLCYL X0A, X1A -- 30.5 -- s Recommend PWH, X0 10 -- -- ns duty ratio of PWL 30% to 70% Input clock pulse width PWLH, X0A -- 15.2 -- s PWLL tCR, External clock Input clock rising/falling time X0, X0A -- -- 5 ns -- tCF operation Main clock -- 1.5 -- 16 MHz fCP operation Internal operating clock frequency Subclock -- -- 8.192 -- kHz fLCP operation External clock tCP -- 62.5 -- 333 ns operation Internal operating clock cycle time Subclock -- -- 122.1 -- s tLCP operation Frequency fluctuation rate f -- -- -- 5 %* locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = | | x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 86 MB90570 Series * X0, X1 clock timing tHCYL 0.8 VCC X0 PWH tCF 0.8 VCC 0.2 VCC PWL tCR 0.2 VCC 0.8 VCC * X0A, X1A clock timing tLCYL 0.8 VCC X0A PWLH tCF 0.8 VCC 0.2 VCC PWLL tCR 0.2 VCC 0.8 VCC * PLL operation guarantee range Relationship between internal operating clock frequency and power supply voltage (V) Operation guarantee range (MB90F574/A) Operation guarantee range MB90574C Power supply voltage VCC 5.5 4.5 PLL operation guarantee range Operation guarantee range MB90V570/A 3.3 3.0 Operation guarantee range MB90573/4 1.5 3 8 12 Internal clock fCP 16 (MHz) Relationship between oscillating frequency, internal operating clock frequency, and power supply voltage (MHz) Multipliedby-4 MultipliedMultiplied-by-2 by-3 16 Multiplied-by-1 12 Internal clock fCP 9 8 6 4 3 2 1.5 3 4 6 8 Oscillation clock FC Not multiplied 12 16 (MHz) 87 MB90570 Series The AC ratings are measured for the following measurement reference voltages. * Input signal waveform Hystheresis input pin 0.8 VCC 0.2 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC * Output signal waveform Hystheresis input pin 2.4 VCC 0.8 VCC (4) Recommended Resonator Manufacturers * Sample application of ceramic resonator X0 R * X1 C1 C2 * Mask ROM product (MB90574) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 CCR7.0MC5 to TDK Corporation CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00 C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in R No required No required No required No required No required No required No required No required (Continued) 88 MB90570 Series (Continued) * Flash product (MB90F574) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 CCR7.0MC5 to TDK Corporation CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00 C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in C2 (pF) 100 100 30 15 5 Built-in Built-in Built-in R No required No required No required No required No required No required No required No required Inquiry: Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.): TEL 65-758-4233 TDK Corporation * TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 * TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 * TDK Singapore (PTE) Ltd.: TEL 65-273-5022 * TDK Hongkong Co., Ltd.: TEL: 852-736-2238 * Korea Branch, TDK Corporation: TEL 82-2-554-6636 (5) Clock Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tCYC CLK 62.5 -- ns -- tCHCL CLK 20 -- ns Parameter Cycle time CLK CLK tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V 89 MB90570 Series (6) Bus Read Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 RD, A23 to A16, AD15 to AD00 A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 ALE, RD ALE, A23 to A16 CLK, A23 to A16, AD15 to AD00 CLK, RD ALE, RD -- -- 0 1 tCP*/2 - 15 1 tCP*/2 - 10 1 tCP*/2 - 20 1 tCP*/2 - 20 1 tCP*/2 - 15 3 tCP*/2 - 60 ns -- -- -- -- -- -- ns ns ns ns ns ns 1 tCP*/2 - 20 1 tCP*/2 - 20 1 tCP*/2 - 15 1 tCP* - 15 -- 3 tCP*/2 - 20 -- -- -- -- ns ns ns ns Parameter ALE pulse width Effective address ALE time ALE address effective time Effective address RD time Effective address valid data input RD pulse width Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH 5 tCP*/2 - 60 ns -- ns RD valid data input tRLDV RD data hold time RD ALE time RD address effective time Effective address CLK time RD CLK time ALE RD time tRHDX tRHLH tRHAX tAVCH tRLCH tALRL * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 90 MB90570 Series tAVCH 2.4 V CLK tRLCH 2.4 V tRHLH ALE RD 0.8 V tAVRL AD23 to AD16 2.4 V 0.8 V tAVDV AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V 0.8 VCC 0.2 VCC Read data tRLDV 2.4 V tLHLL tAVLL 2.4 V 0.8 V tLLAX tRLRH 2.4 V tRHAX 2.4 V 0.8 V tRHDX 0.8 VCC 0.2 VCC 2.4 V 91 MB90570 Series (7) Bus Write Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. WRL, WRH, A23 to A16, AD15 to AD00 WRL, WRH WRL, WRH, AD15 to AD00 WRL, WRH, AD15 to AD00 WRL, WRH, A23 to A16 ALE, WRL CLK, WRH -- 20 1 tCP*/2 - 10 1 tCP*/2 - 15 1 tCP*/2 - 20 -- -- -- -- ns ns ns ns 1 tCP - 15 3 tCP*/2 - 20 3 tCP*/2 - 20 -- -- -- ns ns ns Parameter Effective address WR time WR pulse width Symbol tAVWL tWLWH Write data WR time tDVWH WR data hold time WR address effective time WR ALE time WR CLK time tWHDX tWHAX tWHLH tWLCH * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL WRL, WRH 0.8 V tWHAX 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V tWLWH 2.4 V A23 to A16 Address 92 MB90570 Series (8) Ready Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRYHS RDY 45 -- ns -- RDY 0 -- ns tRYHH Parameter RDY setup time RDY hold time Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. 2.4 V CLK ALE 2.4 V RD/WRL, RD/WRH tRYHS RDY (wait inserted) 0.2 VCC tRYHS 0.2 VCC RDY (wait not inserted) 0.8 VCC 0.8 VCC tRYHH (9) Hold Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. HAK HAK -- 30 1 tCP* 1 tCP* 2 tCP* ns ns Parameter Symbol Pins in floating status tXHAL HAK time HAK pin valid time tHAHV * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 0.8 V tXHAL Pins 2.4 V 0.8 V tHAHV 2.4 V 0.8 V 2.4 V High impedance 93 MB90570 Series (10) UART0 (SCI), UART1 (SCI) Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tSCYC 8 tCP* SCK0 to SCK4 -- ns SCK0 to SCK4, Internal shift clock - 80 80 ns tSLOV SOT0 to SOT4 mode SCK0 to SCK4, CL = 80 pF tIVSH 100 -- ns + 1 TTL for an SIN0 to SIN4 SCK0 to SCK4, output pin 60 -- ns tSHIX SIN0 to SIN4 tSHSL tSLSH tSLOV tIVSH tSHIX SCK0 to SCK4 SCK0 to SCK4 External shift clock mode SCK0 to SCK4, CL = 80 pF SOT0 to SOT4 + 1 TTL for an SCK0 to SCK4, output pin SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 4 tCP* 4 tCP* -- 60 60 -- -- 150 -- -- ns ns ns ns ns Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. 94 MB90570 Series * Internal shift clock mode SCK0 to SCK4 0.8 V tSLOV SOT0 to SOT4 2.4 V 0.2 V tSCYC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN0 to SIN4 * External shift clock mode SCK0 to SCK4 0.2 VCC tSLOV SOT0 to SOT4 tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN0 to SIN4 95 MB90570 Series (11) Timer Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. IN0, IN1 -- 4 tCP* -- ns Parameter Input pulse width Symbol tTIWH, tTIWL * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC IN0, IN1 tTIWH tTIWL (12) Timer Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. OUT0 to OUT3, tTO -- 30 -- ns PPG0, PPG1 Parameter CLK TOUT transition time 2.4 V CLK tTO TOUT 2.4 V 0.8 V 96 MB90570 Series (13) Trigger Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. IRQ0 to IRQ5, -- 5 tCP* tTRGL -- ns ADTG, IN0, IN1 Parameter Input pulse width * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.8 VCC IRQ0 to IRQ5 ADTG, IN0, IN1 tTRGH 0.8 VCC 0.2 VCC tTRGL 0.2 VCC 97 MB90570 Series (14) Chip Select Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. CS0 to CS7, AD15 to AD00 RD, CS0 to CS7 CS0 to CS7, WRL, WRH CLK, CS0 to CS7 -- 1 tCP*/2 - 10 -- 1 tCP*/2 - 10 1 tCP*/2 - 20 -- -- ns ns 5 tCP*/2 - 60 ns -- ns Parameter Valid chip select output Valid data input time RD chip select output effective time WR chip select output effective time Valid chip select output CLK time Symbol tSVDV tRHSV tWHSV tSVCH * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tSVCH CLK 2.4 V RD 2.4 V tRHSV A23 to A16 CS0 to CS7 0.8 V tSVDV AD15 to AD00 2.4 V 0.8 V Read data 2.4 V tWHSV WRL, WRH 2.4 V AD15 to AD00 Write data 98 MB90570 Series (15) I2C Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. -- 62.5 666 ns All products ns Only as master ns ns Only as slave Stop condition detection tSTOI SCL output "L" width SCL output "H" width SDA output delay time Setup after SDA output interrupt period SCL input "L" width SCL input "H" width SDA input setup time SDA input hold time tLOWO SCL tHIGHO tDOO SDA,SCL tDOSUO tLOWI SCL tHIGHI tSUI SDA,SCL tHOI 0 -- ns tCP+40 40 -- -- ns ns 4tCP-20 3tCP+40 -- -- ns ns -- 3tCP+40 -- ns ns Only as master ns ns tCPxmxn/2-20 tCPxmxn/2+20 tCP(mxn/ 2+4)-20 2tCP-20 tCP(mxn/ 2+4)+20 2tCP+20 Parameter Symbol Internal clock cycle time tCP Start condition output Stop condition output tSTAO tSTOO tCPxmxn/2-20 tCPxmxn/2+20 tCP(mxn/ 2+4)-20 3tCP+40 tCP(mxn/ 2+4)+20 -- SDA,SCL Start condition detection tSTAI Notes: * "m" and "n" in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in the clock control register "ICCR". For details, refer to the register description in the hardware manual. * tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL "L" width. * The SDA and SCL output values indicate that rise time is 0 ns. 99 MB90570 Series * I2C interface [data transmitter (master/slave)] tLOWO SCL 0.2 VCC tHIGHO 0.8 VCC 0.8 VCC 0.2 VCC 1 8 tDOO tSUI 9 tHOI tDOSUO 0.8 VCC 0.8 VCC 0.8 VCC tSTAO tDOO SDA ACK * I2C interface [data receiver (master/slave)] tHIGHI SCL 6 tSUI SDA 0.8 VCC 0.8 VCC 0.2 VCC 7 tHOI 0.2 VCC 8 0.2 VCC 9 tDOO tDOO tDOSUO tLOWI 0.8 VCC 0.2 VCC tSTOI ACK 100 MB90570 Series (16) Pulse Width on External Interrupt Pin at Return from STOP Mode (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Input pulse width Symbol tIRQWH tIRQWL Pin name IRQ2 to IRQ7 Condition Value Min. 6tCP Max. Unit ns Remarks * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.80.8 VCC VCC 0.80.8 VCC VCC 0.20.2 VCC VCC tIRQWH tIRQWH tIRQWL tIRQWL 0.20.2 VCC VCC IRQ2 IRQ7 IRQ2 IRQ7 101 MB90570 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Parameter Min. Typ. Max. Resolution -- -- -- 8/10 -- bit Total error -- -- -- -- 5.0 LSB Non-linear error -- -- -- -- 2.5 LSB Differential -- -- -- -- 1.9 LSB linearity error -- Zero transition AN0 to VOT -3.5 LSB +0.5 LSB +4.5 LSB mV voltage AN7 Full-scale AN0 to AVRH AVRH AVRH mV transition VFST AN7 -6.5 LSB -1.5 LSB +1.5 LSB voltage VCC = 5.0 V 10% 352tCP Conversion time -- -- -- -- s at machine clock of 16 MHz VCC = 5.0 V 10% at 64tCP Sampling period -- -- -- -- s machine clock of 6 MHz AN0 to Analog port -- -- 10 A IAIN AN7 input current Analog input AN0 to VAIN AVRL -- AVRH V voltage AN7 AVRL -- -- AVCC -- AVRH V +2.7 Reference voltage AVRH -- AVRL 0 -- V -2.7 AVCC -- 5 -- mA IA CPU stopped and 8/10-bit Power supply A/D converter not in current -- -- 5 A AVCC IAH operation (VCC = AVCC = AVRH = 5.0 V) IR AVRH -- -- 400 -- A Reference CPU stopped and 8/10-bit voltage supply A/D converter not in -- -- 5 A AVRH IRH current operation (VCC = AVCC = AVRH = 5.0 V) Offset between AN0 to -- -- -- -- 4 LSB channels AN7 102 MB90570 Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB {1 LSB x (N - 1) + 0.5 LSB} Digital output 004 003 002 001 VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB 1 LSB = (Theoretical value) AVRH - AVRL 1024 [V] Total error for digital output N = [LSB] VOT (Theoretical value) = AVRL + 0.5 LSB[V] VFST (Theoretical value) = AVRH - 1.5 LSB[V] VNT: Voltage at a transition of digital output from (N - 1) to N (Continued) 103 MB90570 Series (Continued) Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (measured value) N+1 Actual conversion value N Differential linearity error Theoretical characteristics Digital output Digital output VNT 004 003 002 001 Theoretical characteristics VOT (measured value) AVRL Analog input AVRH Actual conversion characteristics N-1 V(N + 1)T (measured value) VNT (measured Actual conversion value N-2 AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB - 1 LSB [LSB] [V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH" 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 7 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model Analog input C0 Comparator C1 MB90573/4, MB90V570/A MB90F574/A MB90574C R 1.5 k, C 30 pF R 3.0 k, C 65 pF Note: Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 104 MB90570 Series 8. D/A Converter Electrical Characteristics (AVCC = VCC = DVCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Symbol Pin name Min. Typ. Max. -- -- -- -- -- -- IDVR IDVRS -- DVCC DVCC DVCC -- -- -- -- -- -- -- -- -- -- -- VSS + 3.0 -- -- -- 8 -- -- -- 10 -- 120 -- 20 -- 0.9 1.2 1.5 20 AVCC 300 10 -- bit LSB % LSB s Load capacitance: 20 pF V A Conversion under no load Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance A In sleep mode k 105 MB90570 Series s EXAMPLE CHARACTERISTICS (1) Power Supply Current (MB90574) ICC (mA) 35 30 ICC - VCC TA = +25C Fc = 16 MHz ICCS (mA) 10 9 8 7 6 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 5 4 3 2 1 ICCS - VCC TA = +25C Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 25 Fc = 12.5 MHz 20 15 10 5 3.0 4.0 ICC - TA VCC = 5.0 V Fc = 16 MHz 25 Fc = 12.5 MHz 20 15 10 5 -20 +10 +40 +70 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 5.0 6.0 VCC (V) ICCS (mA) 10 9 8 7 6 5 4 3 2 1 +100 TA (C) 3.0 4.0 5.0 6.0 VCC (V) ICC (mA) 35 30 ICCS - TA VCC = 5.0 V Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) ICCL (A) 160 140 120 100 80 60 ICCL - VCC TA = +25C Fc = 8 kHz ICCLS (mA) 70 60 50 40 30 20 ICCLS - VCC TA = +25C Fc = 8 kHz 40 20 3.0 4.0 5.0 6.0 VCC (V) 10 3.0 4.0 5.0 6.0 VCC (V) 106 MB90570 Series ICC (mA) 35 30 25 20 15 10 5 ICC - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCS (mA) 10 9 8 7 6 5 4 3 2 1 ICCS - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 4.0 6.0 8.0 12.0 16.0 Fc (MHz) 4.0 6.0 8.0 12.0 16.0 Fc (MHz) ICCT (A) 20 18 16 14 12 10 8 6 4 2 3.0 ICCT - VCC TA = +25C ICCH (A) 10 9 8 Fc = 8 kHz 7 6 5 4 3 2 1 ICCH - VCC TA = +25C 4.0 5.0 6.0 VCC (V) ICCLH (A) 10 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 9 8 7 6 5 4 3 2 1 3.0 4.0 5.0 6.0 VCC (V) ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 ICCT - TA ICCLH - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +40 +70 +100 TA (C) -20 +10 +40 +70 +100 TA (C) 107 MB90570 Series ICCL (A) 20 18 16 14 12 10 8 6 4 2 -20 ICCL - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCLS (A) 14 12 10 8 6 4 2 ICCLS - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) -20 +10 +40 +70 +100 TA (C) (2) Power Supply Current (MB90F574) ICC - VCC ICC (mA) 140 TA = +25C 120 100 80 60 40 20 3.0 ICC (mA) 120 VCC = 5.0 V 100 Fc = 16 MHz 80 Fc = 12.5 MHz 60 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 25 20 15 40 20 10 5 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) 4.0 ICC - TA 5.0 6.0 VCC (V) ICCS (mA) 40 35 30 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz Fc = 16 MHz 35 Fc = 12.5 MHz 30 25 20 15 10 5 3.0 4.0 ICCS - TA 5.0 6.0 VCC (V) Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz ICCS (mA) 40 TA = +25C ICCS - VCC VCC = 5.0 V -20 +10 +40 +70 +100 TA (C) 108 MB90570 Series ICCLS - VCC ICCLS (A) 200 180 160 140 120 100 80 60 40 20 3.0 ICC - FC ICC (mA) 120 TA = +25C 100 80 60 40 20 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 25 20 15 10 5 4.0 8.0 12.0 ICCS (mA) 40 35 30 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 16.0 FC (MHZ) 4.0 5.0 6.0 VCC (V) ICCS - FC FC = 8 kHz TA = +25C TA = +25C 4.0 8.0 12.0 16.0 FC (MHZ) ICCT - VCC ICCT (A) 50 40 FC = 8 kHZ 30 TA = +25C ICCH (A) 10 9 8 7 6 5 20 4 3 10 2 1 3 4 5 6 VCC (V) 3.0 ICCH -VCC TA = +25C 4.0 5.0 6.0 VCC (V) 109 MB90570 Series ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +70 +100 TA (C) ICCLS - TA ICCH (A) 10 9 8 7 6 5 4 3 2 1 -20 ICCH - TA +10 +40 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +70 +100 TA (C) ICCLS (A) 20 18 16 14 12 10 8 6 4 2 -20 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) 110 MB90570 Series (3)Power Supply Current (MB90574C) ICC (mA) 70 60 50 40 30 20 10 0 3.0 3.5 4.0 ICC - VCC TA = +25 C FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz 4.5 5.0 5.5 6.0 VCC (V) ICC (mA) 50 45 40 35 30 25 20 15 10 5 0 -50 ICC - TA VCC = 5.0 V FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz -20 10 40 70 100 TA (C) ICC (mA) 70 60 50 40 30 20 10 0 2 4 6 ICC - FC TA = +25 C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V ICCS (mA) 18 16 14 12 10 8 ICCS - VCC TA = +25 C FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz 8 10 12 14 16 FC (MHz) FC = 5 MHz 6 FC = 4 MHz 4 FC = 2 MHz 2 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V) ICCS (mA) 18 16 14 12 10 8 6 4 2 0 -50 ICCS - TA VCC = 5 V FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 4 MHz FC = 2 MHz -20 10 40 70 100 TA (C) ICCS (mA) 18 16 14 12 10 8 6 4 2 0 2 ICCS - FC TA = +25 C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 4 6 8 10 12 14 16 FC (MHz) 111 MB90570 Series ICCH (A) ICCH - VCC TA = +25 C 10 9 8 7 6 5 4 3 2 1 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V) ICCH (A) 10 9 8 7 6 5 4 3 2 1 0 -50 -20 ICCH - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C) ICCT (A) ICCT - VCC TA = +25 C 10 9 8 7 6 5 4 3 2 1 FC = 8 kHz 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V) ICCT (A) 10 9 8 7 6 5 4 3 2 1 0 -50 -20 ICCT - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C) ICCL (A) 70 60 50 40 30 20 10 ICCL - VCC TA = +25 C ICCL (A) 70 60 50 40 ICCL - TA FC = 8 kHz 30 20 10 0 -50 -20 10 40 70 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 100 TA (C) 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V) 112 MB90570 Series ICCLS (A) 25 20 15 10 5 ICCLS - VCC TA = +25 C ICCLS (A) 25 20 15 ICCLS - TA FC = 8 kHz 10 5 0 -50 -20 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C) 113 MB90570 Series s INSTRUCTIONS (351 INSTRUCTIONS) Table 1 Item Mnemonic # ~ Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction. RG B Operation LH AH I S T N Z V C RMW Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. * Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 114 MB90570 Series Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst 115 MB90570 Series Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * -- @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 0 0 2 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions. 116 MB90570 Series Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing 00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F Listed in tables of instructions 1 2 1 1 2 2 0 0 Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte Cycles Access (c) word Cycles Access (d) long Cycles Access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4 Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 -- Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations. 117 MB90570 Series Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions] RG B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) LH AH I S T N Z V C RMW 3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 Z Z Z Z Z Z Z Z Z Z * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - - 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 118 MB90570 Series Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~ RG B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 LH AH I S T N Z V C RMW 2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 - - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a) 2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d) MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 119 MB90570 Series Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) RG B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) LH AH I S T N Z V C RMW 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - - ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 120 MB90570 Series Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW 2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a) 2 0 2 0 2 0 2 0 4 0 4 0 0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - * - * - * - * - * - * DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3 RG B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32 LH AH I S T N Z V C RMW 0 1 0 0 0 1 0 0 2 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5 Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 121 MB90570 Series Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ * 1 RG B Operation Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (eam) LH AH I S T N Z V C RMW 0 1 0 1 0 0 word (AH) /byte (AL) 0 word (A)/byte (ear) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - *2 A, eam 2+ *3 2 *4 *6 word (A)/byte (eam) 0 long (A)/word (ear) DIVUW A, ear DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10 *7 long (A)/word (eam) 0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A) MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 122 MB90570 Series Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5 RG Mnemonic DIV DIV DIV DIVW DIVW A A, ear B 0 Operation LH AH I S T N Z V C RMW 0 1 0 1 0 A, eam 2 + A, ear A, eam 2 2+ word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * - - - - - MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4: A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 123 MB90570 Series Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] RG B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) LH AH I S T N Z V C RMW 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - * 0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a) NOTW A NOTW ear NOTW eam 0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 124 MB90570 Series Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions] RG B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH I S T N Z V C RMW 2 0 2 0 2 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * R R R R R R - - - - - - - - - - - - XORL A, ea XORL A, eam Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2 Sign Inversion Instructions (Byte/Word) [6 Instructions] RG B 0 Operation byte (A) 0 - (A) LH AH I S T N Z V C RMW 0 2 0 0 2 0 X - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - - * - - * 2 3 2+ 5+ (a) 1 2 0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam 2 3 2+ 5+ (a) 0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0 Normalize Instruction (Long Word) [1 Instruction] Operation LH AH I S T N Z V C RMW long (A) Shift until first digit is "1" - byte (R0) Current shift count - - - - - * - - - *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 125 MB90570 Series Table 18 Mnemonic RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0 Shift Instructions (Byte/Word/Long Word) [18 Instructions] RG # 2 2 ~ 2 2 B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) LH AH I S T N Z V C RMW 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- --- - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * - - - * - * - - - - - - - - - - - - 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2 2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 --* --* --- ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0 word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) --*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * * long (A) Arithmetic right shift (A, R0) - - - *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 126 MB90570 Series Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 1 Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 LH AH I S T N Z V C RMW RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @A addr16 @ear @eam @ear *3 @eam *3 addr24 word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) 2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 (c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c) CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7: 2+ 11+ (a) 4 10 word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23 4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 127 MB90570 Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16 LH AH I S T N Z V C RMW # 3 4 10 ~ * *1 *2 *3 *4 *3 *5 1 RG 0 0 1 0 1 0 2 - - - - - - - - - - - - - - - - ----* ----* - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * - - - - * * * * * * * * * * * * * - - - - - - - * - * - - - - - - ear, #imm8, rel eam, #imm8, rel* CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*10 4 4+ 5 5+ 3 DBNZ DBNZ ear, rel eam, rel 3+ *6 3 *5 Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0 ----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - * *- *- *- *- - - - - * - - - - * DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24 3+ *6 2 3 4 1 1 2 20 16 17 20 15 6 #imm8 -------- UNLINK RET *8 RETP *9 1 1 1 5 4 6 0 0 0 (c) (c) (d) - - - -------- -------- -------- - - - *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 128 MB90570 Series Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 RG B (c) (c) (c) *4 (c) (c) (c) *4 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n LH AH I S T N Z V C RMW 0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - * - - - - - - - - - - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * * 6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8 byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space - - - - - - - - ------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1 ------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - - Z* -- - - - - - - - - - - - - - - Prefix code for no flag change Prefix code for common register bank *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 x (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 129 MB90570 Series Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I S T N Z V C RMW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z Z Z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - 2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 Branch when (addr16:bp) b = 1, bit = 1 SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5: Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 RG B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH I S T N Z V C RMW 0 0 0 0 0 0 - - X - Z - - * - X - Z - - - - - - - - - - - - - - - - - - - - * * R R - - * * * * - - - - - - - - - - - - - - - - - - Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 130 MB90570 Series Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1 2 String Instructions [10 Instructions] Operation LH AH I S T N Z V C RMW RG B * *3 *4 *4 *3 *6 *6 *7 *7 *6 3 * *5 *5 *5 5 Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * * - - * * * - - * * - - - * * - - - * * - - - * * - - - - - - - - - - - 2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8 MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2 2 6m +6 *8 m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 131 MB90570 Series s ORDERING INFORMATION Part number MB90573PFF MB90574PFF MB90F574PFF MB90F574APFF MB90573PFV MB90574PFV MB90574CPFV MB90F574PFV MB90F574APFV MB90574CPMT MB90F574APMT Package 120-pin Plastic LQFP (FPT-120P-M05) Remarks 120-pin Plastic QFP (FPT-120P-M13) 120-pin Plastic LQFP (FPT-120P-M21) 132 MB90570 Series s PACKAGE DIMENSIONS 120-pin plastic LQFP (FPT-120P-M05) 16.000.20(.630.008)SQ 14.000.10(.551.004)SQ 90 61 91 60 0.08(.003) Details of "A" part 1.50 -0.10 +0.20 +.008 (Mounting height) INDEX .059 -.004 120 31 "A" 0~8 LEAD No. 1 30 0.40(.016) 0.160.03 (.006.001) 0.07(.003) M 0.1450.055 (.006.002) 0.500.20 (.020.008) 0.45/0.75 (.018/.030) 0.100.10 (.004.004) (Stand off) 0.25(.010) C 1998 FUJITSU LIMITED F120006S-3C-4 Dimensions in mm (inches) 120-pin plastic QFP (FPT-120P-M13) 90 22.600.20(.890.008)SQ 20.000.10(.787.004)SQ 3.85(.152)MAX (Mounting height) 61 0.05(.002)MIN (STAND OFF) 60 91 14.50 (.571) REF 21.60 (.850) NOM Details of "A" part 0.15(.006) 0.15(.006) INDEX 0.15(.006)MAX 0.40(.016)MAX "A" 1 30 120 31 Details of "B" part 0.1250.05 (.005.002) 0 10 LEAD No. 0.50(.0197) 0.200.10 (.008.004) 0.08(.003) M 0.500.20(.020.008) 0.10(.004) "B" C 2000 FUJITSU LIMITED F120013S-2C-4 Dimensions in mm (inches) 133 MB90570 Series 120-pin plastic LQFP (FPT-120P-M21) 18.000.20(.709.008)SQ 16.000.10(.630.004)SQ 90 61 91 60 0.08(.003) Details of "A" part 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) INDEX "A" 0~8 120 31 LEAD No. 1 30 0.50(.020) 0.220.05 (.009.002) 0.08(.003) M 0.145 .006 +0.05 -0.03 +.002 -.001 0.45/0.75 (.018/.030) 0.100.05 (.004.002) (Stand off) 0.25(.010) Dimensions in mm (inches) C 1998 FUJITSU LIMITED F120033S-2C-2 134 MB90570 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F0101 (c) FUJITSU LIMITED Printed in Japan 136 |
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